Aiwa RC-AAT15, Руководство по обслуживанию

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1 FEO O
Output terminal for focus error amplifier. Internally connected to window comparator input for
bias condition.
2 FEI I Input terminal for focus error.
3 FDFCT I Capacitor connection terminal for time constant used when there is defect.
4 FGD I
This pin is connected to GND via capacitor when high frequency gain of the focus servo is
attenuated.
5 FLB I
This is a pin where the time constant is externally connected to raise the low frequency gain of the
focus servo.
6 FEO O Focus drive output.
7 FEM I Focus amplifier inverted input.
8 SRCH I
This is a pin where the time constant is externally connected to generate the focus search
waveform.
9 TGU I
This is a pin where the selection time constant is externally connected to set the tracking servo the
high frequency gain.
10 TG2 I
This is a pin where the selection time constant is externally connected to set the tracking high
frequency gain.
11 FSET I Pin for setting peak of the phase compensator of the focus tracking.
12 TAM I Tracking amplifier inverted input.
13 TAO O Tracking drive output.
14 SLP I Sled amplifier non-inverted input.
15 SLM I Sled amplifier inverted input.
16 SLO O Sled drive output.
17 ISET I
The current which determines height of the focus search, track jump and sled kick is input with
external resistance connected.
18 VCC I Power supply.
19 LOCK I “L” setting starts sled disorder-prevention circuit. (No pull-up resistance) (Connected to VC)
20 CLK I Clock input for serial data transfer from CPU. (No pull-up resistance)
21 XLT I Latch input from CPU. (No pull-up resistance)
22 DATA I Serial data input from CPU. (No pull-up resistance)
23 XRST I Reset system at “L” setting. (No pull-up resistance)
24 COUT O Signal output for track number counting.
25 SENS1 O
FZC, DFCT1, TZC, BALH, TGH, FOH, or ATSC is output depending on the command from
CPU.
26 SENS2 O DFCT2, MIRR, BALL, TGL or FOL is output depending on the command from CPU.
27 FOK O Output terminal for focus OK comparator.
28 CC2 I Input pin where the DEFECT bottom hold output is capacitance coupled.
29 CC1 O DEFECT bottom-hold output terminal. Internally connected to interruption comparator input.
30 CB I Connection terminal for DEFECT bottom-hold capacitor.
31 CP I Connection terminal for MIRR hold-capacitor. Anti-reverse input terminal for MIRR comparator.
32 RFI I Input terminal by capacity combination of RF summing amplifier.
33 RFO O Output terminal of RF summing amplifier. Checkpoint of Eye pattern.
IC DESCRIPTION
IC, CXA1992AR
Pin No. Pin Name I/O Description
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9 9
2
8 9
4 2
9 8
TEL 13942296513 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL 13942296513 QQ 376315150 892498299 TEL 13942296513 QQ 376315150 892498299
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