SCHEMATIC
THESEUS DUAL OVERDRIVE
7
CH.B OUT
CH.A IN
CH.B IN
CH.A OUT
CHANNEL A
FROM
INPUT
CHANNEL A
FROM
TO
OUTPUT
TO
CHANNEL B
TO
CHANNEL B
FROM
IN
JACK
OUT
IN
JACK
OUT
VA
VC VA
VC
TO
SEND
RETURN
FROM
4k
7
5M
M
1N5817
+9V
100n
BYP_GND
BYP_GND
10
0k
A
25
kB
100kB
1M
GND
10
0R
47k
47
k
GND
100uF
GND
100uF
VB
47k
47
k
100uF
VC
VD
VA
BYP_GND
10
0R
100uF
BYP_GND
GND2 GND2
4k
7
5M
M
BYP_GND
1M
GND2
22
n
TL072P
TL072P
VA
GND
100pF
100k
1M
VB
27k
33k
10
n
10
n
GND
10
k
100n
VB
220k
6k8
VB
1k
10n
VB
6k8
50
kB
10n
VB
1k
VB
1u
F
1u
F
1M
GND
10
0k
A
25
kB
100kB
22
n
TL072P
TL072P
100pF
100k
1M
27k
33k
10
n
10
n
10
k
100n
220k
6k8
1k
10n
6k8
50
kB
10n
1k
1u
F
1u
F
1M
GND2
GND2
GND2
VC
VD
VD
VD
VD
VD
VD
R2
9
LE
D
A
D1
A2
A3
A1
CHANNEL A
B2
B3
B1
C2
C3
C1
2
1
1
3
2
1
4
4
1
6
C23
VO
LU
M
E_
A
1
2
3
TO
NE
_A
1
2
3
DRIVE_A
1
2
3
RP
D1
CHANNEL B
C2
C3
C1
B2
B3
B1
A2
A3
A1
R2
7
R12
R1
3
C21
C10
R25
R2
6
C20
1
4
3
4
R2
8
C22
R3
0
LE
D
B
RP
D2
C1
2
3
1
IC1A
6
5
7
IC1B
8
4
C2
R2
R1
R4
R5
C3
C4
R6
C5
R7
R8
D2
D3
D4
D5
D6
D7
R9
C6
R10
PR
ES
EN
CE
_A
1
2
3
C7
R3
SW_1A
1
2
SW_1B
3
4
SW
_1
C
5
6
SW
_1
D
7
8
SW_1E
9
10
SW_1F
11
12
C8
C9
R1
1
VO
LU
M
E_
B
1
2
3
TO
NE
_B
1
2
3
DRIVE_B
1
2
3
C1
1
6
5
7
IC2B
2
3
1
IC2A
8
4
C12
R15
R1
4
R17
R18
C1
3
C1
4
R1
9
C15
R20
R21
D8
D9
D10
D11
D1
2
D1
3
R22
C16
R23
PR
ES
EN
CE
_B
1
2
3
C17
R16
C1
8
C1
9
R2
4
4
3
