Aim APE1553-1-DS, Руководство по оборудованию

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APE1553-1/2(-DS) Hardware Manual
3.1 PCI Express Interface and BIU-I/O FPGA
The new common FPGA architecture of AIM’s new family of PCI Express based
modules includes both the complete PCI Express bus logic and the BIU processor logic.
The FPGA implements the following features:

PCI Express 1.1 compliant bus interface

Global RAM interface and arbitration

Boot function

SPI controller for update programming

MIL-STD-1553 Encoder

MIL-STD-1553 Decoder

IRIG-B Encoder/Decoder and Timecode Processor

System & Maintenance Controller / RS232 Maintenance Interface

External Trigger Inputs and Outputs

Eight user programmable Discrete I/Os
3.1.1 PCI Express Bus Interface
The PCIe-Interface is an IP-Core implementation compliant with the PCIe-
Standard V1.1. It is a single Lane IP-Core with three BAR-Registers implemented in
the on board FPGA.
3.1.2 Global RAM Interface and Arbitration
The Global RAM Arbiter and the Global RAM interface port are implemented in
the on board FPGA. The Arbiter controls Global RAM access between the participants
(BIU Processors, PCIe, and the Timecode Processor) in a fair arbitration scheme.
3.1.3 SPI Controller for SPI-Flash update programming
The on board FPGA provides an IP-Core SPI-Controller to program/update the on
board SPI-Flash memory.
3.1.4 MIL-STD-1553 Encoder
The MIL-STD-1553 encoder comprises a Manchester Encoder with full error injection
capability. The encoder is used to generate faulty (or fault free) command and data
words on the bus. This encoder allows the user to insert protocol errors as required by
the 'Remote Terminal Production Test Plan'.
3.1.5 MIL-STD-1553 Decoder
The MIL-STD-1553 decoder comprises a Manchester Bi-phase decoding unit which
samples the incoming serial data stream. The decoder detects the synchronization
pattern (Command/Status and Data Sync.), converts 16 bit Manchester encoded serial
data to parallel and receives the parity bit. The decoder indicates the sync. pattern and
error information (parity error, Manchester error, framing error) via dedicated bits in a
readable error register.