40
The Standard Event Status Enable Register provides a mask between the Event Status Register
and the Status Byte Register. If any bit becomes ‘1’ in both registers, then the ESB bit will be set
in the Status Byte Register. This enable register is set by the *ESE
<NRF>
command to a value
0 - 255, and read back by the *ESE? query (which will always return the value last set by the
controller). On power-up it is set to 0.
Execution Error Register (EER)
This instrument specific register contains a number representing the last command processing
error encountered over this interface. The error numbers have the following meaning:
0
No error has occurred since this register was last read.
100
Enable Error:
For some reason the input enable command cannot be executed. The
cause can be determined by reading the Input Trip and State Registers.
101
Numeric Error:
the parameter value sent was outside the permitted range for the
command in the present circumstances.
102
Interruption Error:
the input has been disabled in order to execute a command (e.g.
a mode or range change) which cannot be performed while the input is enabled.
This error can be avoided by turning the input OFF before sending the command.
103
Recall Error:
the store specified in a RECALL command either does not contain valid
data, or is incompatible with the present setting of the 600W mode selection.
200
Access Denied:
an attempt was made to change the instrument’s settings from an
interface which is locked out of write privileges by a lock held by another interface.
The Execution Error Register is read and cleared using the ‘EER?’ command. On power up this
register is set to 0 for all interface instances.
There is no corresponding mask register: if any of these errors occurs, then bit 4 of the Standard
Event Status Register will be set. This bit can be masked from any further consequences by
clearing bit 4 of the Standard Event Status Enable Register.
Status Byte Register (STB) and GPIB Service Request Enable Register (SRE)
These two registers are implemented as required by the IEEE Std. 488.2.
Any bits set in the Status Byte Register which correspond to bits set in the Service Request
Enable Register will cause the RQS/MSS bit to be set in the Status Byte Register, thus
generating a Service Request on the bus.
The Status Byte Register is read either by the *STB? query, which will return MSS in bit 6, or by a
Serial Poll which will return RQS in bit 6. The Service Request Enable register is set by the *SRE
<NRF>
command and read by the *SRE? query.
Bits 7, 3 & 2:
Not used, permanently 0.
Bit 6
MSS/RQS
. This bit (as defined by IEEE Std. 488.2) contains alternatively the
Master Status Summary message returned in response to the *STB? query, or the
Requesting Service message returned in response to a Serial Poll.
The RQS message is cleared when polled, but the MSS bit remains set for as long
as the condition is true.
Bit 5
ESB.
The
Event Status
Bit. This bit is set if any bits set in the Standard Event Status
Register correspond to bits set in the Standard Event Status Enable Register.
Bit 4
MAV.
The
Message Available
Bit. This will be set when the instrument has a
response message formatted and ready to send to the controller.
The bit will be cleared after the Response Message Terminator has been sent.
Bit 1
INTR.
The
Input Trip
Bit. This bit is set if any bits set in the Input Trip Register
correspond to bits set in the Input Trip Enable Register.
Bit 0
INST.
The
Input State
Bit. This bit is set if any bits set in the Input State Register
correspond to bits set in the Input Status Enable Register.
Содержание LD400
Страница 1: ...LD400 LD400P 400W DC Electronic Loads INSTRUCTION MANUAL ...
Страница 54: ...Book Part No 48511 1730 Issue 2 ...
