39
that no longer apply will be cleared; any bit reporting a condition that remains true will remain set.
The Input Trip Enable Register provides the mask between the Input Trip Register and the Status
Byte Register. If any bit becomes ‘1’ in both registers, then the INTR bit (bit 1) will be set in the
Status Byte Register. This enable register is set by the ITE
<NRF>
command to a value 0 - 255,
and read back by the ITE? query (which will always return the value last set by the controller). On
power-up the ITE register is set to 0 and ITR is cleared (but bits it contains may be set after
initialisation in the unusual case of any of the conditions reported being true).
Input State Register
Bit 7
Fault condition:
One or more of the hardware detectors is reporting a fault condition.
Caused by excess temperature, input voltage, internal to external sense voltage
difference, or fan failure.
Bits 6-5
Not used, permanently 0.
Bit 4
Duty cycle protect:
Set in 600W mode if the permitted power and time limit is
exceeded.
If no action is taken, an Over Power Protect Trip will follow 10 seconds later.
Bit 3
Voltage below Dropout:
the load is not conducting current because the source
voltage is below the dropout voltage setting.
Corresponds to the
Dropout
warning in the display.
Bit 2
Input nonlinearity:
the load is not conducting the current expected because the
power limit circuit is restricting it.
Corresponds to the
Power Limit
warning in the display.
Bit 1
Input saturation:
the load cannot conduct the current required because there is
insufficient voltage from the source.
Corresponds to the
Low Voltage
warning in the display.
Bit 0
Input Disabled:
Reports the present state of the input enable setting.
The bits in the Input State Register continually reflect the present state of the condition they
report. The register can be read by the ISR? query, but this does not change the state of the
contents. On power-up it is normally set to 1 (input disabled), unless the power up option on the
Utilities
menu has been set to retain the previous state.
The Input Status Enable register provides a mask between the Input Status Register and the
Status Byte Register. If any bit becomes ‘1’ in both registers, then the INST bit (bit 0) will be set in
the Status Byte Register. This enable register is set by the ISE
<NRF>
command to a value
0 - 255, and read back by the ISE? query (which will always return the value last set by the
controller). On power-up it is set to 0.
Standard Event Status Registers (ESR and ESE)
The Standard Event Status Register is defined by the IEEE Std. 488.2 GPIB standard. It is a bit
field, where each bit is independent and has the following significance:
Bit 7
Power On.
Set when power is first applied to the instrument.
Bits 6, 3 & 1:
Not used, permanently 0.
Bit 5
Command Error.
Set when a syntax error is detected in a command or parameter.
The parser is reset and parsing continues at the next byte in the input stream.
Bit 4
Execution Error.
Set when a non-zero value is written to the Execution Error
register, if a syntactically correct command cannot be executed for any reason.
Bit 2
Query Error.
Set when a query error occurs, because the controller has not issued
commands and read response messages in the correct sequence.
Bit 0
Operation Complete.
Set in response to the ‘*OPC’ command.
The Standard Event Status Register is read and cleared by the *ESR? query, which returns a
decimal number corresponding to the contents. On power-up it is set to 128, to report the
power-on bit.
Содержание LD400
Страница 1: ...LD400 LD400P 400W DC Electronic Loads INSTRUCTION MANUAL ...
Страница 54: ...Book Part No 48511 1730 Issue 2 ...
