Advantech SOM-3569, Руководство пользователя

Страница: 20 / 87

SOM-3569 User Manual 8
1.3.8.12 SMBus
SMBus 2.0 specification. Supports SMBALERT# signal. Signal level 3.3V or 1.8V
selectable.
1.3.8.13 Serial port
2 ports 4-wire HSUART signal interface using RTS/CTS control only
 Programmable FIFO enable/disable
 64B iDMA FIFO per channel with up to 32B burst capability
 Even, odd, or no parity bit selectable
 1, 1.5, or 2 stop bit selectable
1.3.8.14 MIPI
Supports CSI2 image sensors connected using both D-PHY 1.1 and D-PHY 1.2.
SoC has 4 dedicated DPHY1.2 lanes and 2 differential clock lanes, supporting peak
transfer rates of 2.5Gb/s per lane.
1.3.8.15 TPM
Supports TPM 2.0 module by default.
1.3.8.16 BIOS
BIOS chip is on module by default. Also allows users to place a BIOS chip on the car-
rier board with appropriate design and a pull-down to GND on BIOS_DISABLE# pin.
1.3.9 Power Management
1.3.9.1 Power Supply
Supports both ATX and AT power modes. VSB is for suspend power and can be
option if not require standby (suspend-to-RAM) support. RTC Battery may be option
if keep time/date is not require.
 VCC: 5V +/- 5%

VSB: 5V +/- 5% (Suspend power)
 RTC Battery Power: 2.0V - 3.3V
1.3.9.2 PWROK
Power OK from main power supply. A high value indicates that the power is good.
This signal can be used to hold off Module startup to allow Carrier based FPGAs or
other configurable devices time to be programmed.
1.3.9.3 Power Sequence
Refer to Qseven R2.1 electrical specification
1.3.9.4 Wake Event
Various wake-up events supporting allow user to apply into different scenario.
Wake-on-LAN(WOL): Wake to S0 from S3/S4/S5
USB Wake: Wake to S0 from S3
PCIe Device Wake: depends on user inquiry and may need customized BIOS
LPC Wake: depends on user inquiry and may need customized BIOS
Note! If the system COMS is cleared, we strongly suggest to go to the BIOS
setup menu and load default settings on first boot up.