Advantech PCIE-1840, Руководство пользователя

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31 PCIE-1840 User Manual
Appendix B
B
lock Diagram
Figure B.3 Dual ADCs data composition under TIS mode
Figure B.4 Quad ADCs combination architecture in TIS mode
Time Interleaved Sampling (TIS) is a function to increase the sampling rate of PCIE-
1840. It combines multiple ADCs to sample a single input signal. The ADCs in TIS
have the same sampling rate but different clock phase shift. And the acquisition data
from each ADC are interleaved to construct a waveform as like a single ADC dose.
The following figures describe how TIS works.
The mismatches between multiple ADCs will degrade the performance of PCIE-
1840. They will lead to voltage swings in time domain and unexpected spurs in fre-
quency domain. These mismatches include offset mismatch, gain mismatch, and
clock phase mismatch. Though PCIE-1840 is capable to calibrate the gain error
under TIS, the non-perfectly matched ADCs would still degrade the SNR ratio. Users
should take this unavoidable degradation into consideration, especially in frequency
domain applications.