Advantech PCI-1755, Руководство пользователя

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D.2 Counter Read/Write and Control Regist ers
The 82C54 programmable interval timer uses four registers at addresses BASE + 20H ,
BASE + 24H , BASE + 28 H and BASE + 2CH for read, write and control of counter
functions. Register functions appear below:
Register Function
BASE + 20H Counter 0 read/write
BASE + 24H Counter 1 read/write
BASE + 28H Counter 2 read/write
BASE + 2CH Control register
Since the 82C54 counter uses a 16-bit structure, each section of read/write data is split into
a least significant byte (LSB) and most significant byte (MSB). To avoid errors it is
important that you make read/write operations in pairs and keep track of the byte order. The
data format for the control register is as below:
BASE+2CH 82C54 control bit, standard mode
Bit D7 D6 D5 D4 D3 D2 D1 D0
Value SC1 SC0 RW1 RW0 M2 M1 M0 BCD
Description
SC1 & SC0 Select number
Counter
SC1 SC0
0 0 0
1 0 1
2 1 0
Read-back command 1 1
RW1 & RW0 Select read/write operation
Operation
RW1 RW0
Counter latch 0 0
Read/Write LSB 0 1
Read/Write MSB 1 0
Read/Write LSB first,
then MSB 1 1