Advantech PCA-6005, Руководство пользователя

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PCA-6005 User’s Manual 94
A.1.8 List of Registers
Watchdog Timer configuration Registers (LDN = 05h)
Watchdog Timer Control Register (Index = FBh, Default = 00h)
Bit
Description
7 This bit must be set to 0
6-5 Reserved
4 Enable read/write to the game port base address to reset the
WDT counter.0: Disable a read from or write to game port
base address to reset WDT counter (default)1: Enable a read
from or write to game port base address to reset WDT
counter
3 WDT counter unit select0: Minute (default)1: Second
2 Reserved
1 Direct time out controlThis bit is self-cleaning.0: Normal
(default)1: Direct time our regardless of the counter.
0 WDT status0: No time-out after last re-load counter value
(default).1: The timer was time-out.
Watchdog Timer Time-out Value Register (Index = FDh, Default = 00h)
Bit
Description
7-0 Watchdog timer time-out valueWatchdog timer counter time-
out value (1 ~ 256 units)
Game Port Configuration Registers (LDN = 06h)
Game Port Activate (Index = 30h, Default =00h)
Bit
Description
7-1 Reserved
0 Game Port Enable1: Enabled0: Disabled
Game Port Base Address MSB Register (Index = 60h, Default = 02h)
Bit
Description
7-4 Read only with "0h" for Base Address [15:12]
3-0 Game Port Base Address MSBRead/Write, mapped as Base
Address [11:8]
Game Port Base Address LSB Register (Index = 61h, Default = 01h)
Bit
Description