Advantech MIC-3758DIO, Руководство пользователя

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MIC-3758DIO User Manual 38
C.6 Interrupt State Register
Base+0x20/22/24/26: Interrupt state setting.
This register can read and clear the status of the interrupt flag. If an inter-
rupt occurs, you can check the status of 0x40 (refer to C.7) to identify in
which port the interrupt occurred. Then you can read the identified port to
know in which bit an interrupt occurs. If you want to clear the interrupt
flag, just identify in which bit the interrupt occurs and then write “1” into
that bit directly.
Bit 15 - Bit 0 (Read): Read the Interrupt Flag Status
• 1: means an interrupt flag occurs in Pn-IDIm
• 0: means no interrupt flag occurs in Pn-IDIm
(n : 0 to 7 for Port 0 to Port 7, m : 0 to 7 for IDI0 to IDI7 )
To identify in which port an interrupt occurs, please refer to C.7
Bit 15 - Bit 0 (Write): Clear the Interrupt Flag.
• 1: Clear the interrupt flag in Pn-IDIm
• 0: Keep the interrupt flag status in Pn-IDIm
Base+0x20 for Port 1 and Port 0
Base+0x22 for Port 3 and Port 2
Base+0x24 for Port 5 and Port 4
Base+0x26 for Port 7 and Port 6
Base+0x20 - 0x26(Read/Write)
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P1
IDI7
P1
IDI6
P1
IDI5
P1
IDI4
P1
IDI3
P1
IDI2
P1
IDI1
P1
IDI0
P0
IDI7
P0
IDI6
P0
IDI5
P0
IDI4
P0
IDI3
P0
IDI2
P0
IDI1
P0
IDI0