37
Appendix C
C.5 Digital Input Falling Edge Interrupt Register
When the digital input Falling Edge Interrupt is enabled, a 1 to 0 transac-
tion on the input channel will generate a interrupt to the PC. Each digital
input channel has a independent interrupt enable control bit.
Base+0x12/16/1A/1E: Digital Input Falling Edge Interrupt setting
Bit 15 - Bit 0(Write):
• 0: Disable the Pn-IDIm Falling Edge interrupt function
• 1: Enable the Pn-IDIm Falling Edge interrupt function
( n : 0 to 7 for Port 0 to Port 7, m : 0 to 7 for IDI0 to IDI7 )
Bit 15 - Bit 0(Read): Read back the setting value.
Base+0x12 for Port 1 and Port 0
Base+0x16 for Port 3 and Port 2
Base+0x1A for Port 5 and Port 4
Base+0x1E for Port 7 and Port 6
Base+0x12 - 0x1E(Read/Write)
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P1
IDI7
P1
IDI6
P1
IDI5
P1
IDI4
P1
IDI3
P1
IDI2
P1
IDI1
P1
IDI0
P0
IDI7
P0
IDI6
P0
IDI5
P0
IDI4
P0
IDI3
P0
IDI2
P0
IDI1
P0
IDI0
Содержание MIC-3758DIO
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Страница 18: ...MIC 3758DIO User Manual 12...
Страница 21: ...15 Chapter3 Figure 3 2 I O Connector Pin Assignments for MIC 3758DIO...
Страница 33: ...2 APPENDIX A Specifications...
Страница 35: ...2 APPENDIX B Function Block Diagram...
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Страница 37: ...2 APPENDIX C Register Structure Format...