Advantech MIC-3756, Руководство пользователя

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active for only one clock cycle. The other output form, TC Toggle,
uses the trailing edge of TC to toggle a flip-flop to generate an output
level instead of a pulse. The toggle output is 1/2 the frequency of TC.
The TC Toggled output will frequently be used to generate variable
duty-cycle square waves.
Users can clear the Toggled output by writ ing the Count Reset
Register (Base Add. + Eh). If Bit0 of the Count Reset Regis ter is
Logic“1”, write logic“0” into the Bit1 of Count Reset Register, Users
can clear the Toggle output.
Count Source Selection
Counter Mode bits CM3 specify the source used as input to the
counter and the active edge that is counted. Logic“1” counter clock
comes from 1M crystal on board . Logic“0” counter clock come from
DI00 pin.
Gating Control
Counter Mode bits CM1 and CM0 specify the hardware gating options.
When “no gating” is selected (CM1, CM0 = 11), the counter will
proceed unconditionally as long as it is clocked. For any other gating
mode, the count process is conditioned by the specified gating
configuration. The gating source comes from DI16. The Gate is level
sensitive. When it goes low, counting is simply suspended until the
Gate goes high again. When “DI16 as GATE high” is selected (CM1,
CM0 = 01), counting can proceed only when the Gate source is logical
high level. When “DI16 as GATE low” is selected (CM1, CM0 = 10),