Advantech IDK-1107WP Series, Руководство пользователя

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IDK-1107WP User Manual 14
Note: Output signals from any system shall be low or Hi-Z state when VDD is off.
3.3 Interface Timing
3.3.1 Timing Characteristics
Note1: Frame rate is 60 Hz.
Note2: Since this assembly is operated in DE only mode, Hsync and Vsync input
signals should be set to low logic level. Otherwise, this assembly would
operate abnormally.
B7 Blue Data 7 (MSB)
Blue-pixel Data
Each blue pixel’s brightness data consists of
these 8 bits pixel data.
B6 Blue Data 6
B5 Blue Data 5
B4 Blue Data 4
B3 Blue Data 3
B2 Blue Data 2
B1 Blue Data 1
B0 Blue Data 0 (LSB)
RxCLKIN-
LVDS Clock Input
DE Display Enable
VS Vertical Sync
HS Horizontal Sync
Table 3.2: Timing Characteristics
Parameter Symbol Min. Typ. Max. Unit Condition
Clock frequency 1/ T
Clock
27 29.5 33 MHz
Vertical
Section
Period T
V
490 500 550
T
H
Active T
VD
480
Blanking T
VB
10 20 70
Horizontal
Section
Period T
H
930 992 1090
T
Clock
Active T
HD
800
Blanking T
HB
130 192 290