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ADLINK Technology SMARC LEC-PX30, Руководство пользователя

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ADLINK Technology Inc. 

LEC-

PX30   User’s Guide

 

 

Page 40 

copyright © 2020 ADLINK Technology Inc.   

 

 

4.4

 

SMARC pin to controller mapping 

 

Pin 

SMARC  
Signal Name 

Module 
Direction 

Module 
Termination 

Type/Tolerance 

Controller 

Controller  
Pin Name 

I/O Mux 
default 

Power Rail 

P1 

SMB_ALERT_1V8# 

- 

- 

- 

- 

- 

-

 

- 

P2 

GND 

- 

- 

- 

- 

- 

-

 

- 

P3 

 

In 

- 

CSI 

PX30 

MIPI_CSI_CLKP 

-

 

VCC_1V0 

P4 

CSI1_CK- 

In 

- 

CSI 

PX30 

MIPI_CSI_CLKN 

-

 

VCC_1V0 

P5 

GBE1_SDP 

- 

- 

- 

- 

 

-

 

- 

P6 

GBE0_SDP 

- 

- 

- 

- 

 

-

 

- 

P7 

C 

In 

- 

CSI 

PX30 

MIPI_CSI_DP0 

-

 

VCC_1V0 

P8 

CSI1_RX0- 

In 

- 

CSI 

PX30 

MIPI_CSI_DN0 

-

 

VCC_1V0 

P9 

GND 

- 

- 

- 

- 

 

-

 

- 

P10 

C 

In 

- 

CSI 

PX30 

MIPI_CSI_DP1 

-

 

VCC_1V0 

P11 

CSI1_RX1- 

In 

- 

CSI 

PX30 

MIPI_CSI_DN1 

-

 

VCC_1V0 

P12 

GND 

- 

- 

- 

- 

 

-

 

- 

P13 

C 

In 

- 

CSI 

PX30 

MIPI_CSI_DP2 

-

 

VCC_1V0 

P14 

CSI1_RX2- 

In 

- 

CSI 

PX30 

MIPI_CSI_DN2 

-

 

VCC_1V0 

P15 

GND 

- 

- 

- 

- 

- 

-

 

- 

P16 

C 

In 

- 

CSI 

PX30 

MIPI_CSI_DP3 

-

 

VCC_1V0 

P17 

CSI1_RX3- 

In 

- 

CSI 

PX30 

MIPI_CSI_DN3 

-

 

VCC_1V0 

P18 

GND 

- 

- 

- 

- 

- 

-

 

- 

P19 

GBE0_MDI3- 

- 

- 

- 

- 

- 

-

 

- 

P20 

GB 

- 

- 

- 

- 

- 

-

 

- 

P21 

GBE0_LINK100# 

Out/OD 

- 

- 

DP83822 

LED_1 

-

 

VCC3V3_SYS 

P22 

GBE0_LINK1000# 

- 

- 

- 

- 

- 

-

 

- 

P23 

GBE0_MDI2- 

- 

- 

- 

- 

- 

-

 

- 

P24 

GB 

- 

- 

- 

- 

- 

-

 

- 

P25 

GBE0_LINK_ACT# 

Out/OD 

- 

- 

DP83822 

LED_0 

-

 

VCC3V3_SYS 

P26 

GBE0_MDI1- 

Bi-Dir 

- 

- 

DP83822 

RD_M 

-

 

3.3VA1 

P27 

GB 

Bi-Dir 

- 

- 

DP83822 

RD_P 

-

 

3.3VA1 

Содержание SMARC LEC-PX30

Страница 1: ...LEC PX30 User s Guide 22 01 2020 Rev 0 7 Corrected engineering version...

Страница 2: ......

Страница 3: ...scriptions at any time without notice Environmental Responsibility ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European Uni...

Страница 4: ...umidity Keep equipment properly ventilated do not block or cover ventilation openings Make sure to use recommended voltage and power source settings Always install and operate equipment near an easily...

Страница 5: ...ARC Rev 2 1 Page 3 copyright 2020 ADLINK Technology Inc Revision History Revision Description Date Author 0 6 Engineering version 22 8 2019 JB 0 7 Corrected engineering version mechanical and SMARC to...

Страница 6: ...2 9 Power 12 2 10 Mechanical and Environmental 13 3 Block Diagram 14 4 Pinout and Signal Descriptions 15 4 1 Pin Summary 15 4 2 Signal Terminology Descriptions 19 4 3 Signal Description by function 20...

Страница 7: ...Inc 4 3 17 Boot Select 38 4 3 18 Power 39 4 4 SMARC pin to controller mapping 40 5 Software Support 51 5 1 1 Early Access 51 5 1 2 Yocto 51 5 1 3 Ubuntu 51 6 Mechanical and Thermal 52 6 1 Module dimen...

Страница 8: ...nology Inc LEC PX30 User s Guide Page 6 copyright 2020 ADLINK Technology Inc List of Figures Figure 1 Module function diagram 14 Figure 2 Module top botom side pin numbering 15 Figure 3 Heatspreader H...

Страница 9: ...under 6W Two Module sizes are defined 82 mm x 50 mm and 82 mm x 80 mm The Module PCBs have 314 edge fingers that mate with a low profile 314 pin 0 5 mm pitch right angle connector the connector is som...

Страница 10: ...C L2 Cache 256KB unified system L2 cache IoT security CryptoAuthentication Device Microchip ATECC608A Cryptographic co processor with secure hardware based key storage for sign verify authentication p...

Страница 11: ...Supports DirectX 11 FL9_3 OpenGLES 1 1 2 0 3 2 Vulkan 1 0 OpenCL 2 0 Full Profile Video decoding H 264 up to 1080p 60fps H 265 HEVC up to 1080p 60fps MPEG 4 ISO IEC 14496 2 SP L0 3 ASP L0 5 up to 108...

Страница 12: ...LAN MAC 10 100 Ethernet Controller on SoC Supports 10 100 Mbps data transfer rates both full duplex and half duplex Secondary LAN MAC PHY 10 100 Ethernet Controller on LAN9514 via USB 2 0 Supports 10...

Страница 13: ...cupied by SPI to CAN controller I2S 2x I2S interfaces with audio resolution from 16 bits to 32 bits and sample rate up to 192KHz see Audio Codec support I2C Four I2C interfaces Support for 7 bit and 1...

Страница 14: ...ation 4 41 4 51 5 0 and 5 1 2 7 SEMA Board Management Controller Voltage current monitoring boot configuration logistics and forensic information flat panel control watchdog timer 2 8 Debug Header 30...

Страница 15: ...under approval by SGET Dimension SMARC short size module 82mm x 50mm Operating Temperature Standard 0 C to 60 C Rugged 20 C to 85 C optional Humidity 5 90 RH operating non condensing 5 95 RH storage a...

Страница 16: ...3L x16 DDR3L x16 PHY 10 100Mbps CAN FD PMIC Crypto Auth ATECC608A RTC eMCC 8 16 32 64GB Watchdog Boot Select Power Control LAN9514 DSI0 LVDS0 CSI1 SDIO USB0 USB1 USB2 USB3 USB4 GbE0 GbE1 UART0 UART1 C...

Страница 17: ...4 1 Pin Summary The below table is a comprehensible list of all signal pins on the MXM 3 connector in the standard specification SMARC 2 1 Those signals not supported on LEC PX30 are strikethrough ST...

Страница 18: ...SERDES_1_TX P30 GBE0_MDI0 S31 GBE1_LINK_ACT P31 SPI0_CS1 S32 PCIE_D_RX SERDES_1_RX P32 GND S33 PCIE_D_RX SERDES_1_RX P33 SDIO_WP S34 GND P34 SDIO_CMD S35 USB4 P Pin Primary Top Side S Pin Secondary B...

Страница 19: ...04 USB3_OTG_ID P104 HDMI_HPD DP1_HPD S105 DP0_AUX P105 HDMI_CTRL_CK DP1_AUX S106 DP0_AUX P106 HDMI_CTRL_DAT DP1_AUX S107 LCD1_BKLT_EN P107 DP1_AUX_SEL S108 LVDS1_CK eDP1_AUX DSI1_CLK P108 GPIO0 CAM0_P...

Страница 20: ...145 WDT_TIME_OUT P145 CAN1_TX S146 PCIE_WAKE P146 CAN1_RX S147 VDD_RTC P147 VDD_IN S148 LID P148 VDD_IN S149 SLEEP P149 VDD_IN S150 VIN_PWR_BAD P150 VDD_IN S151 CHARGING P151 VDD_IN S152 CHARGER_PRSNT...

Страница 21: ...l for MIPI CSI 2 cameras and DSI displays LVDS M PHY Low Voltage Differential Signal for MIPI CSI 3 cameras LVDS LCD Low Voltage Differential Signal for LCD displays LVDS PCIE Low Voltage Differential...

Страница 22: ...S1_1 LVDS1_2 LVDS1_2 LVDS1_3 LVDS1_3 DSI1_D0 DSI1_D0 DSI1_D1 DSI1_D1 DSI1_D2 DSI1_D2 DSI1_D3 DSI1_D3 eDP1_TX0 eDP1_TX0 eDP1_TX1 eDP1_TX1 eDP1_TX2 eDP1_TX2 eDP1_TX3 eDP1_TX3 S134 S135 LVDS0_CK LVDS0_CK...

Страница 23: ...S135 Primary LVDS channel differential pair clock lines O LVDS LCD Runtime LCD0_VDD_EN S133 Primary LVDS channel power enable active high O CMOS 1 8V Runtime LCD0_BKLT_EN S127 Primary LVDS channel ba...

Страница 24: ...ifferential pair clock lines O LVDS D PHY Runtime LCD0_VDD_EN S133 Primary panel power enable active high O CMOS 1 8V Runtime LCD0_BKLT_EN S127 Primary panel backlight enable active high O CMOS 1 8V R...

Страница 25: ...DP1_LANE3 S105 HDMI_CTRL_CK DP1_AUX S106 HDMI_CTRL_DAT DP1_AUX P104 HDMI_HPD DP1_HPD P107 DP1_AUX_SEL All the below signals on Third Interface are not supported Pin DP signal names P92 P93 P95 P96 P9...

Страница 26: ..._TX S2 I2C data for serial camera data support link or differential data lane I O OD CMOS O LVDS M PHY 1 8V Runtime PU 2 2K MIPI CSI 2 0 mode uses I2C_CAM1_DAT MIPI CSI 3 0 mode uses CSI1_TX I2C_CAM1_...

Страница 27: ...I O CMOS 1 8V Runtime Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode I2S2_LRCK HDA_SYNC S50 I2S2 Left Right synchronization clock I O CMOS 1 8V Runtime Module Output i...

Страница 28: ...P65 P66 USB differential data pairs for port 1 I O USB USB Runtime From USB HUB alternatively USB HUB can be removed and USB 2 0 Host directly routed to SOC USB1_EN_OC P67 USB over current sense for p...

Страница 29: ...sb 3 3V Runtime PU 10k Pulled low by Module OD driver to disable USB0 power Pulled low by Carrier OD driver to indicate over current situation USB3_VBUS_DET S37 USB port 3 host power detection when th...

Страница 30: ...y Inc LEC PX30 User s Guide Page 28 copyright 2020 ADLINK Technology Inc 4 3 6 PCIe and SerDes pin sharing 4 3 6 1 PCIe Ports This design does not support PCIe ports 4 3 7 SATA This design does not su...

Страница 31: ...ion LED for GBE 0 1000Mbps O OD CMOS 3 3V Runtime Shall be able to sink 24mA or more Carrier LED current GBE0_LINK_ACT P25 Link Activity Indication LED Driven low on Link 10 100 mbps Blinks on Activit...

Страница 32: ...3V Runtime Shall be able to sink 24mA or more Carrier LED current GBE1_LINK_ACT S31 Link Activity Indication LED Driven low on Link 10 100 mbps Blinks on Activity O OD CMOS 3 3V Runtime Shall be able...

Страница 33: ...onse This signal is used for card initialization and for command transfers During initialization mode this signal is open drain During command transfer this signal is in push pull mode I O CMOS 1 8V o...

Страница 34: ...untime also referred to as MISO SPI0_DO P46 SPI0 Master output Slave input O CMOS 1 8V Runtime also referred to as MOSI SPI1_CS0 P54 SPI1 Master Chip Select 0 O CMOS 1 8V Runtime SPI1_CS1 P55 SPI1 Mas...

Страница 35: ...DTS GPIO4 HDA_RST P112 General purpose I O pin 4 I O CMOS 1 8V Runtime PU 470K on the Module GPIO5 PWM_OUT P113 General purpose I O pin 5 I O CMOS 1 8V Runtime PU 470K on the Module Default is GPIO mo...

Страница 36: ...shake line for port 0 I CMOS 1 8V Runtime SER1_TX P134 Asynchronous serial data output port 1 O CMOS 1 8V Runtime SER1_RX P135 Asynchronous serial data input port 1 I CMOS 1 8V Runtime SER2_TX P136 As...

Страница 37: ...scellaneous Name Pin Description I O Type I O Level Power Domain PU PD Comments TEST S157 Held low by Carrier to invoke Module vendor specific test function s I CMOS 1 8 to 5 Vsb 5 25V Runtime PU on M...

Страница 38: ...D CMOS TBD Standby PU 68K Driven by OD on Carrier Pulled up on module VIN_PWR_BAD S150 Power bad indication from Carrier board Module and Carrier power supplies other than Module and Carrier power sup...

Страница 39: ...es low to force a Module reset floats the line otherwise I OD CMOS TBD Standby PU 10K Driven by OD on Carrier Pulled up on module I2C_PM_DAT P122 Power management I2C bus DATA I O OD CMOS TBD Standby...

Страница 40: ...OS 1 8V Runtime PU 10K Driven by OD on Carrier Pulled up on module Low on this pin allows non protected segments of Module boot device to be rewritten restored from an external USB Host on Module USB0...

Страница 41: ...GND P2 P9 P12 P15 P18 P32 P38 P47 P50 P53 P59 P68 P79 P82 P85 P88 P91 P94 P97 P100 P103 P120 P133 P142 S3 S10 S16 S25 S34 S47 S61 S64 S67 S70 S73 S80 S83 S86 S89 S92 S101 S110 S119 S124 S130 S136 S14...

Страница 42: ...CSI_DP0 VCC_1V0 P8 CSI1_RX0 In CSI PX30 MIPI_CSI_DN0 VCC_1V0 P9 GND P10 CSI1_RX1 In CSI PX30 MIPI_CSI_DP1 VCC_1V0 P11 CSI1_RX1 In CSI PX30 MIPI_CSI_DN1 VCC_1V0 P12 GND P13 CSI1_RX2 In CSI PX30 MIPI_CS...

Страница 43: ...8 P41 SDIO_D2 Bi Dir CMOS VDD_IO PX30 SDMMC0_D2 ALT0 ALT0 VCCIO_SD_1V8 P42 SDIO_D3 Bi Dir CMOS VDD_IO PX30 SDMMC0_D3 ALT0 ALT0 VCCIO_SD_1V8 P43 SPI0_CS0 Out CMOS VDD_IO PX30 SPI0_CSN ALT2 ALT2 VCCIO_F...

Страница 44: ...BDM2 P67 USB1_EN_OC In PU 10K CMOS VDD_IO LAN9514 PRTCTL2 3 3V P68 GND P69 USB2 Bi Dir USB LAN9514 USBDP3 P70 USB2 Bi Dir USB LAN9514 USBDM3 P71 USB2_EN_OC Bi Dir PU 10K CMOS VDD_IO LAN9514 PRTCTL3 3...

Страница 45: ...3_C3_d ALT5 ALT5 VCC1V8_DVP P112 GPIO4 HDA_RST Bi Dir PU 470K CMOS VDD_IO PX30 GPIO3_C4_d VCC1V8_DVP P113 GPIO5 PWM_OUT Bi Dir PU 470K CMOS VDD_IO PX30 GPIO3_C5_d VCC1V8_DVP P114 GPIO6 TACHIN Bi Dir P...

Страница 46: ...1_RX P136 SER2_TX Out CMOS VDD_IO PX30 UART1_TX ALT4 ALT4 VCC_1V8 P137 SER2_RX In CMOS VDD_IO PX30 UART1_RX ALT4 ALT4 VCC_1V8 P138 SER2_RTS Out CMOS VDD_IO PX30 UART1_RTS ALT4 ALT4 VCC_1V8 P139 SER2_C...

Страница 47: ...RX0 S12 CSI0_RX0 S13 GND S14 CSI0_RX1 S15 CSI0_RX1 S16 GND S17 GBE1_MDI0 Bi Dir LAN9514 TXP S18 GBE1_MDI0 Bi Dir LAN9514 TXN S19 GBE1_LINK100 Out OD LAN9514 nSPD_LED VCC3V3_SYS S20 GBE1_MDI1 Bi Dir LA...

Страница 48: ...CK Bi Dir CMOS VDD_IO PX30 I2S1_2CH_SCKL VCC_1V8 S43 ESPI_ALERT0 S44 ESPI_ALERT1 S45 MDIO_CLK S46 MDIO_DAT S47 GND S48 I2C_GP_CK Out PU 2 2K PX30 I2C1_SCL ALT6 ALT6 VCC_1V8 S49 I2C_GP_DAT Bi Dir PU 2...

Страница 49: ...S73 GND S74 USB2_SSRX S75 USB2_SSRX S76 PCIE_B_RST S77 PCIE_C_RST S78 PCIE_C_RX SERDES_2_RX S79 PCIE_C_RX SERDES_2_RX S80 GND S81 PCIE_C_TX SERDES_2_TX S82 PCIE_C_TX SERDES_2_TX S83 GND S84 PCIE_B_RE...

Страница 50: ...S109 LVDS1_CK eDP1_AUX DSI1_CLK S110 GND S111 LVDS1_0 eDP1_TX0 DSI1_D0 S112 LVDS1_0 eDP1_TX0 DSI1_D0 S113 eDP1_HPD DSI1_TE S114 LVDS1_1 eDP1_TX1 DSI1_D1 S115 LVDS1_1 eDP1_TX1 DSI1_D1 S116 LCD1_VDD_EN...

Страница 51: ...LVDS0_CK eDP0_AUX DSI0_CLK Out LVDS PX30 LVDS_CLKP MIPI_DSI S135 LVDS0_CK eDP0_AUX DSI0_CLK Out LVDS PX30 LVDS_CLKN MIPI_DSI S136 GND S137 LVDS0_3 eDP0_TX3 DSI0_D3 Out LVDS PX30 LVDS_TX3P MIPI_DSI S13...

Страница 52: ...Page 50 copyright 2020 ADLINK Technology Inc S151 CHARGING Out PU 68K CMOS VDD_IO PX30 GPIO1_C5_d ALT5 ALT5 VCC_1V8 S152 CHARGER_PRSNT Out PU 100K CMOS VDD_IO PX30 GPIO1_C6_u ALT5 ALT5 VCC_1V8 S153 C...

Страница 53: ...LEC PX30 User s Guide SGET SMARC Rev 2 1 Page 51 copyright 2020 ADLINK Technology Inc 5 Software Support 5 1 1 Early Access 5 1 2 Yocto 5 1 3 Ubuntu...

Страница 54: ...ADLINK Technology Inc LEC PX30 User s Guide Page 52 copyright 2020 ADLINK Technology Inc 6 Mechanical and Thermal 6 1 Module dimensions...

Страница 55: ...User s Guide SGET SMARC Rev 2 1 Page 53 copyright 2020 ADLINK Technology Inc 14 68 9 24 4 34 4 74 82 42 3 6 2 7mm x 4pcs M3 x 4pcs 6 2 Thermal Solutions 6 2 1 Heatspreader HTS Figure 3 Heatspreader H...

Страница 56: ...ADLINK Technology Inc LEC PX30 User s Guide Page 54 copyright 2020 ADLINK Technology Inc 6 2 2 Heatsink THS 4 74 4 34 82 42 3 12 2 7mm x 4pcs Figure 4 Heatsink THS sPX30...

Страница 57: ...LEC PX30 User s Guide SGET SMARC Rev 2 1 Page 55 copyright 2020 ADLINK Technology Inc...

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