ADLINK Technology Q7-BT, Техническое описание

Страница: 28 / 50

22 Interfaces
115 eDP0_TX3- (option) / LVDS_A3-
(LVDS primary channel differential pair 3.
Embedded Display Port primary channel
differential pair 3.)
116 LVDS_B3- (LVDS secondary channel
differential pair 3.)
117 GND 118 GND
119 e (option) / LVD
(LVDS primary channel differential pair
clock lines.
Embedded Display Port primary auxiliary
channel.)
120 LVD (LVDS secondary channel
differential pair clock lines.)
121 eDP0_AUX- (option) / LVDS_A_CLK-
(LVDS primary channel differential pair
clock lines.
Embedded Display Port primary auxiliary
channel.)
122 LVDS_B_CLK- (LVDS secondary channel
differential pair clock lines.)
123 LVDS_BLT_CTRL (Primary functionality
is to control the panel backlight
brightness via pulse width modulation
[PWM].) 124 GP_1-Wire Bus (General Purpose 1-Wire
bus interface. Can be used for consumer
electronics control bus (CEC) of HDMI)
125 LVDS_DID_DAT
(Primary functionality DisplayID DDC
data line used for LVDS flat panel
detection.) 126 LVDS_BLC_DAT (Control data signal for
external SSC clock chip.)
127 LVDS_DID_CLK (Primary functionality is
DisplayID DDC clock line used for LVDS
flat panel detection.) 128 LVDS_BLC_CLK (Control clock signal for
external SSC clock chip.)
129 Not Connected 130 Not Connected
131 D/T (DisplayPort
differential pair lines lane 3, shared with
TMDS differential pair clock lines.) 132 Not Connected
133 DP_LANE3-/TMDS_CLK- (DisplayPort
differential pair lines lane 3, shared with
TMDS differential pair clock lines.) 134 Not Connected
135 GND 136 GND
137 D/TMD
(DisplayPort differential pair lines lane 1,
shared with TMDS differential pair lines
lane 1.) 138 D (Auxiliary channel used for link
management and device control.
Differential pair lines.)
139 DP_LANE1-/TMDS_LANE1-
(DisplayPort differential pair lines lane 1,
shared with TMDS differential pair lines
lane 1.) 140 DDI1_AUX- (Auxiliary channel used for link
management and device control.
Differential pair lines.)
141 GND 142 GND
143 D/TMD
(DisplayPort differential pair lines lane 2,
shared with TMDS differential pair lines
lane 0.) 144 Not Connected
145 DP_LANE2-/TMDS_LANE0-
(DisplayPort differential pair lines lane 2,
shared with TMDS differential pair lines
lane 0.) 146 Not Connected
Table 3-1: Q7 Interface (GF1) Signal Descriptions (Continued)
Pin # Primary (Top Side) Pin # Secondary (Bottom Side)