ADLINK Technology PCI-8254, Руководство пользователя

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Motion Control Theory 169
PCI-8254 / PCI-8258
There are two levels of FIFO buffer design contained in controller
and hardware to accelerate compare speed. The hardware FIFO
can have 255 records with compare speed up to 1 MHz. The
controller contains 999 FIFO buffers and execute points filling in
operation in every motion control cycle. You can input point array
of any size in the APS function library (limited by system memory
size). The APS function library shall load all compare points to the
controller dynamically. No extra program coding is required for
loading compare point dynamically in the controller even in case of
many compare points.
APIs for loading compare table array:
APS_set_trigger_table ();
Figure 4-69: Table compare trigger block diagram
Inside PCI-8254 / PCI-8258
APS driver
memory
Table
array
Point 1~Point n
Hardware
FIFO
Kernel memory
FIFO