ADLINK Technology NuPRO-865, Руководство пользователя

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Award BIOS Setup
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41
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Timing Selectable
X CAS Latency Time
X Active to Precharge Delay
X DRAM RAS# to CAS# Delay
X DRAM RAS# Precharge
Memory Frequency For
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole At 15M-16M
AGP Aperture Size (MB)
Init Display First
**On-Chip VGA Setting**
On-Chip VGA
On-Chip Frame Buffer Size
By SPD
2
6
3
3
Auto
Enabled
Disabled
Disabled
128
Onboard/AGP
.
Enabled
8MB
Item Help
__________________________
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Menu Level
¾
↑↓→←
Move Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
F5: Previous Values F6: Fail-safe defaults F7: Optimized Defaults
DRAM Timing Selectable:
Select the operating system that is selecting DRAM timing, so select SPD for setting
SDRAM timing by SPD.
Options: Manual, By SPD
CAS Latency Time:
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing.
Options: 2, 2.5, and 3.
Active To Precharge Delay:
Select the operating system that is active to precharge delay.
Options: 5, 6, 7, 8.
DRAM RAS# to CAS# Delay:
You can select RAS to CAS Delay time in HCLKs of 2/2 or 3/3.
The system board designer should set the values in this field, depending on the DRAM
installed. Do not change the values in this field unless the specifications of the installed
DRAM or the installed CPU are also changed.
Options: 2, 3, 4.
DRAM RAS# Precharge:
If an insufficient number of cycles are allowed for the RAS to accumulate its charge before