ADLINK Technology NuDAQ PCI-9812/10, Руководство пользователя

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Registers Format
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21
4.8 FIFO Status Register
This register is used to monitor some status of the PCI-9812/10.
Address: BASE + 18h
Attribute:
read
Data Format:
Bit 7 6 5 4 3 2 1 0
BASE+18h --- --- ACQ TD PTCO FIFOOR FIFOHF FIFOIR
BASE+19h --- --- --- --- --- --- --- ---
BASE+1Ah --- --- --- --- --- --- --- ---
BASE+1Bh --- --- --- --- --- --- --- ---
bit 0 -- FIFOIR, FIFO input ready flag .
0: The FIFO is not ready for input, which means the FIFO is full
1: The FIFO is ready for input (not full).
bit 1 -- FIFOHF, FIFO half full flag.
0: The FIFO is not half full yet.
1: The FIFO is at least half full.
bit 2 -- FIFOOR, FIFO output ready flag
0: The FIFO is not ready for output, which means the FIFO is
empty.
1: The FIFO is ready for output (not empty).
bit 3 -- PTC0, post trigger counter is 0
0: The post trigger counter is not 0.
1: The post trigger counter reaches 0.
bit 4 -- TD, trigger detection flag
0: The trigger condition is not met yet, no trigger is detected.
1: Trigger is detected.
bit 5 -- ACQ, acquisition flag
0: The PCI-9812/10 is not acquiring data. Maybe the card is
disabled or the card is waiting for trigger.
1: The PCI-9812/10 is acquiring data.
bit 6..31 -- don't card