ADLINK Technology NuDAQ PCI-9812/10, Руководство пользователя

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Registers Format
4
Registers Format
The detailed descriptions of the register form at and structure of the
PCI-9812/10 are specified in this chapter. This information is useful
for the programmer who wants to handle the card using low-level
programming.
4.1 I/O Port Address
The PCI-9812/10 functions as 32-bit PCI target device to any
master on the PCI bus. It supports burst transfer to memory space
by using 32-bit data. So, both data read and write will be based on
32-bit data transfer. The Table 4.1 shows the I/O address of each
register with respect to the base address. The function of each
register also is shown.
I/O Address Read Write
Base + 0 ------------- ADC Channel Enable Reg.
Base + 4 ------------- ADC Clock Divisor Reg.
Base + 8 ------------- Trigger Mode Reg.
Base + C ------------- Trigger Level Reg.
Base + 10 ------------- Trigger Source Reg.
Base + 14 ------------- Post Trigger Counter Reg.
Base + 18 FIFO Control & Status Reg. FIFO Control & Status Reg.
Base + 1C ------------- Acquisition Enable Reg.
Base + 20 ------------- Clock Source Register
Table 4.1 I/O Address