ADLINK Technology NuDAQ DIN-96DI, Руководство пользователя

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Operation Theorem
Mode 3 X 2 ~P2C0 falling edge of P2C0
Mode 4 X 3 Timer Output Timer count down to 0
Table 4.1 ISC register format
Default settings
When the IRQ sources is set as “P1C0 OR ~P1C3” or “P2C0 OR
~P2C3”, the IRQ trigger conditions are summarized in Table 4.2,
P1C0 P1C3 IRQ Trigger Condition
High X P1C0=‘H’ disable all IRQ
X Low P1C3=‘L’ disable all IRQ
Low 1->0 P1C3 falling edge trigger when P1C0=L
0->1 High P1C0 rising edge trigger when P1C3=H
P2C0 P2C3 IRQ Trigger Condition
High X P2C0=‘H’ disable all IRQ
X Low P2C3=‘L’ disable all IRQ
Low 1->0 P2C3 falling edge trigger when P2C0=L
0->1 High P2C0 rising edge trigger when P2C3=H
Table 4.2 IRQ Trigger conditions
By using the four signals: P1C0, P2C0, P1C3, and P2C3, user can
utilize their combination to generate a proper IRQ for versatile
applications.
4.3.5 Change of State (COS) Interrupt
What is COS?
The COS (Change of State) means when the input state (logic level) is
changed from low to high, or from high to low. The COS detection
circuit will detect the edge of level change. In the PCI-7396 card, the
COS detection circuit is applied to all the input channels. When any
channel changes its logic level, the COS detection circuit generates
an interrupt request to PCI controller.
P2A0
COS1
COS2
INT1
P1A0
Clear_IRQ Clear_IRQ Clear_IRQ