ADLINK Technology M-855 Series, Руководство пользователя

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BIOS Setup
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Select the operating system that is selecting DRAM timing, so select SPD for setting
SDRAM timing by SPD.
The choices: Manual, By SPD.
CAS Latency Time:
When synchronous DRAM is installed, the number of clock cycles of CAS latency
depends on the DRAM timing.
The choices: 2, 2.5.
Active To Precharge Delay:
Select the operating system that is active to precharge delay.
The choices: 5, 6, 7.
DRAM RAS# To CAS# Delay:
This field lets you insert a timing delay between the CAS and RAS strobe signals,
used when DRAM is written to, read from, or refreshed. Fast gives faster
performance; and Slow gives more stable performance. This field applies only when
synchronous DRAM is installed in the system.
The choices: 2, 3.
DRAM RAS# Precharge:
If an insufficient number of cycles are allowed for the RAS to accumulate its charge
before DRAM refresh, the refresh may be incomplete and the DRAM may fail to
retain data. Fast gives faster performance; and Slow gives more stable performance.
This field applies only when synchronous DRAM is installed in the system.
The choices: 2, 3.
DRAM Data Integrity Mode:
This item shows you if the DRAM has ECC or not.
The choices: Non-ECC, ECC.
MGM Core Frequency:
This item allows you to determine the MGM core frequency.
The choices: Auto Max 266MHz, 400/266/133/200MHz,
400/200/100/200MHz, 400/200/100/133MHz,
400/266/133/267MHz, 400/333/166/250MHz,
Auto Max 400/333.
System BIOS Cacheable:
Selecting “Enabled” allows caching of the system BIOS ROM at F0000h-FFFFFh,
resulting in better system performance. However, if any program writes to this
memory area, a system error may result.