ADLINK Technology Express-KL, Руководство пользователя

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BIOS Setup
Feature Options Description
Number of Presets to test 7, 3, 5
0 – 9
Auto
Choose between 7,3,5 and 0-9. Auto = current default
for CPU
Allow PERST# GPIO Usage
Enabled
Disable
Enable/Disable GPIO-based resets to PEG
endpoint(s) during margin search, if needed
SW EQ Enable VOC Jitter Only Test Mode
Jitter & VOC Test
Mode
Auto
Select Jitter & VOC test mode (default) or Jitter only
test mode. Auto will current default (Enabled)
Jitter Dwell Time
3000
PEG Gen3 Preset Search dwell time [0..65535] in
[usec]
Jitter Error Target
2
The margin search error target value [1..65535]
VOC Dwell Time
10000
The VOC margin search dwell time [0..65535] in
[usec]
VOC Error Target
2
The VOC margin search error target value [1..65535]
Generate BDAT PEG Margin
Data
Disabled
Enabled
Enable to generate BDAT PCIe margin tables
PCIe Rx CEM Test Mode
Disabled
Enabled
Enable/Disable PEG Rx CEM Loopback Mode
PCIe Spread Spectrum Clocking
Enabled
Disable
Allows disabling of Spread Spectrum Clocking for
compliance testing
7.3.8. Super IO
Feature Options Description
Super IO Chip Info only
W83627DHG Super IO Configuration Info only
Serial Port 1 Configuration
Serial
Port
Device
Settings
Change
Settings
Enabled
Disabled
IO=3F8h; IRQ=4
Auto
IO=3F8h; IRQ=4
IO=3F8h; IRQ=3,4,5,6,7,10,11,12
IO=2F8h; IRQ=3,4,5,6,7,10,11,12
IO=3E8h; IRQ=3,4,5,6,7,10,11,12
IO=2E8h; IRQ=3,4,5,6,7,10,11,12
Enable/Disable Serial Port (COM).
Fixed configuration of serial port.
Select an optimal setting for Super IO
device.
Serial Port 2 Configuration
Serial
Port
Device
Settings
Change
Settings
Enabled
Disabled
IO=2F8h; IRQ=4
Auto
IO=2F8h; IRQ=3
Enable/Disable Serial Port (COM).
Fixed configuration of serial port.
Select an optimal setting for Super IO
device.