ADLINK Technology CoreModule 730, Справочное руководство

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Chapter 3 Hardware
22 Reference Manual CoreModule 730
Note: The shaded areas denote power or ground.
LVDS Interface
Table 3-8 describes the pin signals of the LVDS interface, which uses a 20-pin, right-angle header with 2
rows, odd/even sequence (1, 2), and 0.079" (2mm) pitch.
Note: The shaded areas denote power or ground.
9 VSYNC Vertical Sync – This signal is used for the digital vertical sync output to
the CRT.
10 PWR Power – Provided through fuse (F1) to +5 volts +/- 5%. F1 is next to J7
header on board.
11 DDC_DATA Display Data Channel - Data
12 DDC_CLK Display Data Channel - Data
Table 3-8. LVDS Interface Pin/Signal Descriptions (J8)
Pin # Signal Description Line
1 VCC_INTRV +12V source
2 VCC_LVDS_CONN JP2 = +3.3 or +5V source
3 GND Ground Gnd
4 GND Ground
5 L Clock Positive Output Clk
6 LVDS_CLK- Clock Negative Output
7 LV Data 3 Positive Output 3
8 LVDS_DAT3- Data 3 Negative Output
9 LV Data 2 Positive Output 2
10 LVDS_DAT2- Data 2 Negative Output
11 LV Data 1 Positive Output 1
12 LVDS_DAT1- Data 1 Negative Output
13 LV Data 0 Positive Output 0
14 LVDS_DAT0- Data 0 Negative Output
15 LVDS_BKLT_CTRL Backlight Control
16 LVDS_VDD_EN LCD Enable
17 LVDS_DDC_CLK Clock
18 LVDS_DDC_DATA Data
19 LVDS_BKLT_EN Backlight Enable
20 NC Not connected
Table 3-7. VGA Interface Pin Signals (J7) (Continued)