Express-BL
Page 19
3.3.
AB Signal Descriptions
3.3.1.
Audio Signals
Signal
Pin #
Description
I/O
PU/PD
Comment
AC_RST# /
HDA_RST#
A30
Reset output to CODEC, active low.
O 3.3VSB
AC_SYNC /
HDA_SYNC
A29 Sample-synchronization signal to the CODEC(s).
O 3.3VSB
AC_BITCLK /
HDA_BITCLK
A32
Serial data clock generated by the external
CODEC(s).
I/O 3.3VSB
AC _SDOUT /
HDA_SDOUT
A33
Serial TDM data output to the CODEC.
O 3.3VSB
PD 15K
Boot strap pin, no external pull-up or
pull-down resistor on carrier board is
recommended to avoid change the
configuration of this signal
AC _SDIN[2:0]
HDA_SDIN[2:0]
B28
B29
B30
Serial TDM data inputs from up to 3 CODECs.
I 3.3VSB
AC_SDIN0: supported
AC_SDIN1: supported
AC_SDIN2: supported
3.3.2.
Analog VGA
Signal
Pin # Description
I/O
PU/PD
Comment
VGA_RED
B89
Red for monitor.
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
O Analog
PD 150R
shall also be terminated on the
carrier with 150
Ω
resistor to
ground close to VGA connector
VGA_GRN
B91
Green for monitor
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
O Analog
PD 150R
shall also be terminated on the
carrier with 150
Ω
resistor to
ground close to VGA connector
VGA_BLU
B92
Blue for monitor.
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
O Analog
PD 150R
shall also be terminated on the
carrier with 150
Ω
resistor to
ground close to VGA connector
VGA_HSYNC
B93
Horizontal sync output to VGA monitor
O 5V
VGA_VSYNC
B94
Vertical sync output to VGA monitor
O 5V
VGA_I2C_CK
B95
DDC clock line (I²C port dedicated to identify
VGA monitor capabilities)
I/O OD 3.3V
PU 2k2 3.3V
VGA_I2C_DAT
B96
DDC data line.
I/O OD 3.3V
PU 2k2 3.3V
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