30
PowerLab Owner’s Guide
Figure A–3
Block diagram of the
PowerLab/16
SP
voltage exceeds 2.9 volts. This signal is fed to circuitry that notifies
the CPU that an external trigger event has been detected. The CPU
then carries out the task for which the trigger is being used (such as
pre-triggering or post-triggering). When the trigger threshold is
crossed, the indicator beside the trigger connector glows yellow.
Two 14-bit DACs (digital-to-analog converters) are used to control the
analog outputs of the PowerLab (marked ‘Output 1’ and ‘Output 2’
on the front panel). The DACs produce waveforms under software
control that are fed through an attenuation network to produce
different full-scale ranges. The signals are then buffered by a power
50/60Hz
MAINS
SYNC
POWER
SUPPLY
A
A
SCSI PORT
Ext Trigger
Digital Output
Digital Input
LATCH
LATCH
16-BIT ADC
Analog Input Channels
FIFO
FIFO
Analog Output
DAC
DAC
SCSI
Controller
SYSTEM GLUE
& REAL-TIME
CLOCK
SAMPLING
CONTROL
GLUE
FIFO
LATCH
LATCH
Multiplexer
USB Port
MC68340
CPU
I2C Port
RAM
I2C
Controller
ROM
USB
Controller
Analog Output
External Trigger
Analog Input
Содержание PowerLab/16SP
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