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Core1553BRM Demonstration Design
2 0
– 115,200 bits per second
– 8 data bit
– Parity set to none
– 1 stop bit
– Flow control set to none
Running the Demonstration Design in Script Mode
1. Turn the power switch SW7 on the board to the ON position.
2. Press RESET (RSTN) to restart the core. Once initialized, HyperTerminal will display the
following:
Core1553BRM NL00 0409-1
– N indicates the design is configured in Non-Initialization/Script mode.
– L indicates that bus loopback is enabled.
– 00 indicates the remote terminal address is set to 00.
Note: If the display shows any other message, check the DIP switch settings.
3. Press ESC to enter command mode ( Figure 2-6 ).
4. From the Transfer menu, choose Send Text File . Browse to select the script file demo_log.txt
(available in the script folder of the Core1553BRM_DEV_KIT_DS.zip file), and click Open to
start the download.
The demo_log.txt script programs one Core1553BRM as the BC and the other as RT 1,
initializes the RT memory tables and sets up the BC to do a BC-to-RT, RT-to-BC, and RT
Figure 2-6 • HyperTerminal Window in Command Mode