INDUSTRIAL I/O PACK SERIES AVME9630/9660 VMEbus 3U/6U CARRIER BOARDS
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Identification PROM - (Read Only, 32 Odd-Byte Addresses)
Each IP contains an identification (ID) PROM that resides in
the ID space per the IP specification. This area of memory
contains 32 bytes of information at most. Both fixed and variable
information may be present within the ID PROM. Fixed information
includes the "IPAC" identifier, model number, and manufacturer's
identification codes. Variable information may include unique
information required for the module. The identification Section for
each IP module is located in the carrier board memory map per
Table 3.1. ID PROM bytes are addressed using only the odd
addresses in a 64-byte block. The ID PROM contents are shown
in Table 3.2 for a generic IP. Refer to the documentation of your IP
module for specific information.
Table 3.2: Generic IP Module ID Space Identification (ID) PROM
Hex Offset
From ID PROM
Base Address
ASCII
Character
Equivalent
Numeric
Value
(Hex)
Field
Description
01
I
49
All IP modules
have
03 P
50
‘IPAC’
05 A
41
07 C
43
09
A3
Acromag
ID
Code
0B
mm
IP
Model
Code
1
0D
00
Not
Used
(Revision)
0F
00
Reserved
11
00
Not
Used
(Driver ID Low
Byte)
13
00
Not
Used
(Driver ID High
Byte)
15
nn
Total
Number
of ID PROM
Bytes
17
cc
CRC
19 to (2*nn - 1)
xx
IP Specific
Space
(2*nn + 1) to 3F
yy
Not Used
Notes (Table 3.2):
1. The IP model number is represented by a two-digit code within
the ID PROM (e.g. the IP405 model is represented by 01 Hex).
Carrier Board Status Register - (Read/Write, Base + C1H)
The Carrier Board Status Register reflects and controls
functions globally on the carrier board.
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
D0
ACE
1
Not
Used
Not
Used
Soft
Reset
GIE
2
GlP
3
Not
Used
Not
Used
Notes:
1.
ACE – this bit is Auto Clear Interrupt Enable.
2.
GIE – this bit is a Global Interrupt Enable.
3.
GIP – this bit is Global Interrupt Pending.
Where:
Bits 7
Writing a “1” to this bit will enable
automatic clear of pending interrupts on
the carrier. When this bit is set pending
interrupts will not be latched or
registered on the carrier. An interrupt
will only remain set as pending on the
carrier if its corresponding IP module
has an active interrupt request.
Bits 6, 5
Not used - equal "0" if read
Bit 4
Software Reset
(Write)
Writing a "1" to this bit causes a
software reset. Writing "0" or reading
the bit has no effect. When set the
software reset bit will have a duration of
1us.
Reset Condition: Set to "0".
Bit 3
Global Interrupt
Enable (GIE)
(Read/Write)
Writing a "1" to this bit enables
interrupts to be serviced, provided that
interrupts are supported and configured.
A "0" disables servicing interrupts.
Reset Condition: Set to "0", interrupts
disabled.
Bit 2
Global Interrupt
Pending (GIP)
(Read)
This bit will be "1" when there is an
interrupt pending. This bit will be "0"
when there is no interrupt pending.
Polling this bit will reflect the board's
pending interrupt status, even if the
Global Interrupt Enable bit is set to "0".
Reset condition: Set to "0".
Bits 1, 0
Not used - equal "0" if read
Interrupt Level Register - (Read/Write, Base + C3H)
The carrier board passes interrupt requests from the IP
modules to the VMEbus. It does not originate interrupt requests.
The Interrupt Level Register allows the user to control the mapping
of IP interrupt requests to the desired VMEbus interrupt level. Note
that the “Global Interrupt Enable” bit in the Carrier Board Status
Register must be set for interrupts to be enabled from the carrier
board. Also, the specific IP interrupt request must be enabled via
its corresponding bit in the Interrupt Enable Register, described
subsequently.
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
D0
Not
Used
Not
Used
Not
Used
Not
Used
Not
Used
IL2 IL1 IL0
Where:
Bits 7,6,5,4,3
Not used - equal "0" if read
Bits 2,1,0
IL2-IL0 (Read/Write)
These bits control the VMEbus interrupt
request level associated with IP
interrupt requests as illustrated in the
next table.
Reset Condition: Set to "0", no interrupt
request.
VMEbus Interrupt Level
IL2
IL1
IL0
None 0
0
0
1 0
0
1
2 0
1
0
3 0
1
1
4 1
0
0
5 1
0
1
6 1
1
0
7 1
1
1
