INDUSTRIAL I/O PACK SERIES AVME9630/9660 VMEbus 3U/6U CARRIER BOARDS
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- 10 -
IP Interrupt Enable Register - (Read/Write, Base + E1H)
The IP Interrupt Enable Register is used to individually
enable/disable IP interrupts. Each IP A through D may have up to
two requests. Note that the "Global Interrupt Enable" bit in the
Carrier Board Status Register must be set for interrupts to be
enabled from the carrier board. The user must also configure the
VMEbus interrupt level using the Interrupt Level Register. If
multiple IP interrupt sources are enabled, they will be serviced in
order from highest to lowest priority with bit 0 (IP A Int0) having the
highest priority and bit 7 (IP D Int1) having the lowest priority.
MSB
D7
Lowest
Priority
D6
D5
D4
D3
D2
D1
LSB
D0
Highest
Priority
IP D
Int1*
Ena
IP D
Int0
*
Ena
IP C
Int1*
Ena
IP C
Int0*
Ena
IP B
Int1
Ena
IP B
Int0
Ena
IP A
Int1
Ena
IP A
Int0
Ena
* Bits not used on AVME9630.
Where:
All Bits
IP Interrupt Enable
(Read/Write)
Writing a "1" to a bit enables interrupts for
the corresponding IP module and interrupt
level. A zero disables the corresponding
interrupt.
Reset Condition: Set to "0", IP interrupts
disabled.
IP Interrupt Pending Register - (Read, Base + E3H)
The IP Interrupt Pending Register is used to individually
identify pending IP interrupts. If multiple IP interrupts are pending,
they will be serviced in order from highest to lowest priority with bit
0 (IP A Int0) having the highest priority and bit 7 (IP D Int1) having
the lowest priority.
MSB
D7
Low
Prior.
D6
D5
D4
D3
D2
D1
LSB
D0
High
Prior.
IP D
Int1*
Pend
IP D
Int0*
Pend
IP C
Int1*
Pend
IP C
Int0*
Pend
IP B
Int1
Pend
IP B
Int0
Pend
IP A
Int1
Pen
d
IP A
Int0
Pen
d
* Bits not used on AVME9630.
Where:
All Bits
IP Interrupt Pending
(Read)
A bit will be a “1” when the corresponding
IP interrupt is pending. A bit will be a “0”
when its corresponding interrupt is not
pending. Polling this bit will reflect the IP
modules pending interrupt status, even if
the IP interrupt enable bit is set to “0”.
Reset Condition: Set to "0".
IP Interrupt Clear Register - (Write, Base + E5H)
The IP Interrupt Clear Register is used to individually clear the
IP interrupt Pending bits set in the IP Interrupt Pending register.
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
D0
IP D
Int1*
Clear
IP D
Int0*
Clear
IP C
Int1*
Clear
IP C
Int0*
Clear
IP B
Int1
Clear
IP B
Int0
Clear
IP A
Int1
Clear
IP A
Int0
Clear
* Bits not used on AVME9630.
Where:
All Bits
IP Interrupt Clear
(Write)
Writing a “1” to a bit causes the
corresponding IP interrupt Pending bit to
clear. Writing “0” or reading has no effect.
Reset Condition: Set to "0".
GENERAL PROGRAMMING CONSIDERATIONS
The carrier board register architecture makes the configuration
fast and easy. The only set of configuration hardware jumpers is
for the base address of the carrier board in the VMEbus short I/O
space. Once the carrier board is mapped to the desired base
address, communication with its registers and the I/O and ID
spaces of the IP modules is straightforward. The carrier board is
easily configured to communicate with IP memory space, if
present, through two configuration registers. Interrupt
configuration/control, if supported by IP modules, is also easily
done through registers.
Board Diagnostics
The board is a non-intelligent slave and does not perform self
diagnostics. It does, however, provide front panel LED's to indicate
successful communication with each of the four IP modules, A
through D (C & D are not used on AVME9630). These LED's are
driven by the corresponding IP acknowledge signal which is
lengthened by circuitry on the carrier board to make the access
visible to the user. This means that frequent accesses to an IP will
result in constant LED illumination. The LED's indicate I/O,
memory, interrupt acknowledge, and ID PROM accesses. Note
that the LED's will not illuminate during accesses of carrier board
registers, or accesses to IP modules which are not physically
present, or to unsupported memory space. The LEDs may
temporarily illuminate upon initial power-up. Additional information
about the error status of the IP modules can be obtained by
reading the IP Error Register.
