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Kungsgatan 12 | SE-411 19 Goteborg | Sweden

+46 31 7758650 | www.caes.com/gaisler

GR-VPX-XCKU060 Carrier Board

GR-VPX-XCKU060

GR-VPX-XCKU060-DSUM
Mar 2022, Version 1.1

Features

•

Xilinx XCKU060, in 1517 pin FCBGA package

•

GR716B (initially with GR716A)

microcontroller

•

SODIMM DDR3 up to 8 GiB

•

SPI flash for FPGA configuration (512 Mbit),

for GR716 boot (256 Mbit), and for data

(256 Mbit)

•

Power, Reset, Clock and Auxiliary circuits

•

Three FMC Mezzanine expansion connectors

•

Scrubbing interface for FPGA

•

Backplane I/F: SpaceWire (control),

SpaceFibre (data), VPX utility management

•

Frontplane I/F and drivers: 4x SpaceFibre,

2x SpaceWire, USB/FTDI UART/JTAG Links,

USB I/F to FMC

•

OpenVPX compatible, 6U format, Payload

profile

Description

The GR-VPX-XCKU060 board features a Xilinx

Kintex Ultrascale XCKU060 FPGA and a

GR716 microcontroller acting as a supervisor

for the FPGA. The board is equipped with

three VITA 57.1 FMC connectors. It can be
operated without any Mezzanine board but is

specifically designed to be used with 1 to 3

GR-HPCB-FMC-M2 Mezzanine Boards

connected, each with a

Myriad™ 2 M2450

Processor. The GR-HPCB-FMC-M2 boards are

not included with the GR-VPX-XCKU060
board.

Specifications

•

System frequency GR716 uC: 20MHz, FPGA

XCKU060: 50 MHz

•

5 x SpaceFibre links rated @ 3.125 Gbps

and 2 x SpaceWire links @ 200 Mbps

•

CIF and LCD data interfaces 16-bit

running at 150 MHz. 24-bit interface
tested allowing upper bound 1.44Gb/s

full-duplex data transfer

•

Typical power consumption <10W (excluding

mezzanines)

•

DC supply via OpenVPX backplane connector

or via +5V/12V DC header for stand-alone

use

Applications

The board is a commercial development board for

prototyping of high-performance application such as:

•

Earth Observation optical and radar payload

processing

•

Multi- and hyperspectral data compression

•

Visual-Based Navigation acceleration

•

Video processing

•

AI/ML processing, such as:

Image segmentation (e.g. cloud
screening and removal)

Object detection (e.g. fire detection)

Pose estimation

The applications can be allocated to the on-board

FPGA or shared with technology implemented in up

to three Mezzanine boards, configured either for
increased performance or for redundancy

applications. The control and supervision of the

FPGA and Mezzanine boards is handled by a rad-

hard microcontroller.

Data She

et & User

Manual

Data She

et & User

Manual

Data She

et & User

Manual

Data She

et & User

Manual

Содержание GR-VPX-XCKU060

Страница 1: ...Processor The GR HPCB FMC M2 boards are not included with the GR VPX XCKU060 board Specifications System frequency GR716 uC 20MHz FPGA XCKU060 50 MHz 5 x SpaceFibre links rated 3 125 Gbps and 2 x Spac...

Страница 2: ...1 compliance 7 4 Functional Blocks 8 4 1 Memory 8 4 2 Xilinx Kintex Ultrascale FPGA 8 4 3 GR716 microcontroller 9 4 4 Oscillators and Clock Inputs 9 4 5 Reset Circuits 10 4 6 Power Supply and Voltage...

Страница 3: ...N 32 5 12 16 PWR GOOD 32 5 12 17 S 3 0 32 5 12 18 I2C 33 5 13 VPX Backplane Interface 33 5 14 Power 40 5 15 Headers 40 5 15 1 J11 FPGA JTAG 40 5 15 2 J12 Power 40 5 15 3 J13 Optional SM bus 41 5 15 4...

Страница 4: ...l the requirements of standard VITA57 1 for FMC Carrier boards RD3 Figure 1 GR VPX XCKU060 Carrier Board 1 2 Reference Documents RD1 https www xilinx com products silicon devices fpga kintex ultrascal...

Страница 5: ...ion 1 0 2022 01 31 First approved issue 1 1 2022 03 09 Page 1 Sec 1 2 Editorial corrections of Applications and RD references 1 4 Abbreviations ASIC Application Specific Integrated Circuit DCDC DC DC...

Страница 6: ...the FMC interfaces are primarily assigned to accommodate this mezzanine board RD8 The pin definitions have been assigned to follow the assignment of the VITA57 1 speci fication RD3 for FMC mezzanine b...

Страница 7: ...the rules in the VITA 57 1 FMC standard RD3 Due to constraints on the Mezzanine board RD8 it was designed for there are some deviations to the rules and recommendations listed below VADJ is fixed to...

Страница 8: ...onfiguration 512Mbit Cypress Spansion S25FL512S DDR3 for FPGA working memory Up to 8 GB SODIMM 204 connector 64bit inter face SPI Flash for GR716 boot data PROM 256Mbit S25FL256L SPI Flash for GR716 d...

Страница 9: ...onnection to FTDI USB circuit Application UART connection to FTDI USB circuit Redundant CMOS SPW1 pins connected to backplane via LVDS transceivers LVDS interface configured as SPW0 I2C slave connecti...

Страница 10: ...pplied with two clocks for general use CLK1 is a 50 MHz 1 8V oscillator soldered onto the board and CLK2 is a DIL 8 pin socket for a user de fined 3 3 V oscillator A 300 MHz LVDS oscillator is dedicat...

Страница 11: ...ch GR HPCB FMC_M2 mezzanine is a reset input controlled by the FPGA 4 6 Power Supply and Voltage Regulation 4 6 1 Overview The power supply system of the GR VPX XCKU060 board requires many voltages to...

Страница 12: ...e 4 6 2 Power sequencing Power sequencing is required for the FPGA power rails The only power domain that is active by default will be the PM_3V3 which provides the power for the GR716 and the Power M...

Страница 13: ...he power good signal PG_C2M Before delivery of the board the UCD9090 is programmed with a default configuration file that specifies such things as rail sequencing order sequencing delays and over unde...

Страница 14: ...s board Figure 7 UCD9090 PMBUS Sequencer circuit 4 6 3 FMC Power Supplies This board has three FMC slots for interface expansion In a fully VITA57 1 compliant design this would require each slot to ha...

Страница 15: ...ed Similarly a fully compliant VITA57 1 compliant design would require VIO_M2C VREF_A_M2C VREF_B_M2C signals connecting from each FMC connector to the FPGA I O banks to allow full flexibility in the a...

Страница 16: ...cated on the front panel are illustrated and listed below Figure 10 Front panel Table 3 Front panel electrical interfaces Interface Marking PCB id Connected to Protocol SpaceFibre SPFI 0 J3 FPGA bank...

Страница 17: ...nction LED power on PWR D1 3V3 supply 3 3V on LED FPGA done DONE D2 FPGA bank 0 pin AF11 FPGA initiation done LED User 0 USR0 D3 FPGA bank 65 pin AF15 FPGA User controlled LED User 1 USR1 D4 FPGA bank...

Страница 18: ...5 V power is provided and the on board generated PM_3V3 rail is above a threshold Note that PM_3V3 sup plies power sequencer see Figure 7 All on board generated secondary supplies are above a thresho...

Страница 19: ...PR_SPFI_4 P1 col 4 Redundant Data Interface 9 X1Y15 228 3 DPN_SPFI_1 P1 col 5 Nominal Data Interface 10 X1Y14 228 2 DPN_SPFI_2 P1 col 6 Nominal Data Interface 11 X1Y13 228 1 DPN_SPFI_3 P1 col 7 Nomina...

Страница 20: ...r 4 It is connected as MGTREFCLK0 of bank 226 This is the centre bank of the RS power supply group see Figure 1 6 in RD9 and can therefore supply a clock for all these banks see section Reference Cloc...

Страница 21: ...6U_SV P1 Control Plane Interface prime P4 Control Plane Interface for 6U backplane P4 Control Plane Interface for 6U backplane Each interface requires 4 LVDS pairs 8 pins Although the FPGAand GR716 ha...

Страница 22: ...ata Memory Memory interface GR716 uC FPGA Control interface GR716 uC Slave 0 FMC1 Slave 1 FMC2 Slave 2 FMC3 Shared SPI interface for FMC1 FMC2 FMC3 with separate Slave Selects The FPGA requires an SPI...

Страница 23: ...KU060 GR VPX XCKU060 DSUM Mar 2022 Version 1 1 and CLK signals but with one of four dedicated SPI Select signals A second SPI interface is connected between the GR716 and FPGA for exchange of con trol...

Страница 24: ...identified between the following elements Table 14 List of I2C interfaces Master Slave Function FPGA FMC1 Control Interface for FMC1 FPGA FMC2 Control Interface for FMC2 FPGA FMC3 Control Interface fo...

Страница 25: ...the FTDI USB interface to allow an external JTAG DSU connection to the FPGA This interface operates with 3 3V logic levels For debugging and direct JTAG programming using Xilinx tools a dedicated con...

Страница 26: ...1 FMC 2 and FMC 3 are LPC low pin count interface compatible However to make the interface compatible with the use of the GR HPCB FMC M2 board some additional signals on the HPC section of the connect...

Страница 27: ...60 DSUM Mar 2022 Version 1 1 GA 1 0 I2C power measurement IC s FMC Power 12V Discrete Signals ENABLE PWR GOOD S 3 0 FMC Auxiliary I2C FMC EEPROM The pinouts for the three connectors are illustrated in...

Страница 28: ...Cobham Gaisler AB Kungsgatan 12 SE 411 19 Goteborg Sweden 46 31 7758650 www caes com gaisler 28 GR VPX XCKU060 GR VPX XCKU060 DSUM Mar 2022 Version 1 1 Figure 17 P2 FMC connector pinout...

Страница 29: ...29 GR VPX XCKU060 GR VPX XCKU060 DSUM Mar 2022 Version 1 1 Figure 18 P3 FMC connector pinout 5 12 3 LCD This is a data interface between the M2 and the FPGA on the Carrier Board comprising 29 signals...

Страница 30: ...M2 This interface is a signal control interface with the GR716 on the Carrier Board as Master These signals on the M2 use 1 8V signalling logic However the SPI interface of the GR716 uses 3 3V signall...

Страница 31: ...nted on the Mezzanine board as shown in RD8 This circuit performs an or of the following conditions and holds the M2 processor RE SETN input low if any of the conditions are low PWR GOOD from power su...

Страница 32: ...to use these pins in order that software running on the M2 can identify which to slot it is attached 5 12 14 12V This is the main power input for the board For further information see RD8 5 12 15 ENA...

Страница 33: ...udes a 2k I2C EEPROM that holds information about the Mezzanine board and its capabilities The data format and record contents are defined by the VITA57 1 standard This I2C interface is connected to t...

Страница 34: ...nal to Cross point switch 1 x CP redundant to SPW1 in GR716 4 x SPFI links each link 2 differential pairs 4 pins 2 x DP nominal to GTH transceivers in FPGA 2 x DP redundant to GTH transceivers in FPGA...

Страница 35: ...5 Row A SM1 SM1 GR716 I2C P0 6 Row G GA3 N C Not used P0 6 Row F GA2 N C Not used P0 6 Row E GND GND P0 6 Row D 12V_Aux N C Not used P0 6 Row C GND GND P0 6 Row B GA1 N C Not used P0 6 Row A GA0 N C N...

Страница 36: ...roller Red P1 4 Row E DP01 T3 PL1N SCR DPL3 T P SpFi DP Lane 3 PL Sys Controller Red P1 4 Row D GND P1 4 Row C DP01 R3 SCR PL1N DPL3 R N SpFi DP Lane 3 Sys Controller Red PL P1 4 Row B DP01 R3 SCR PL1...

Страница 37: ...P1 12 Row B DP03 R3 N C P1 12 Row A GND P1 13 Row G UD P1 13 Row F GND P1 13 Row E DP04 T0 See Use col Connect to switch HPCB config N C V78 3U config SpW SCR signal CPr_SpW_3U_SV P1 13 Row D DP04 T0...

Страница 38: ...UD P4 3 Row C GND P4 3 Row B UD P4 3 Row A UD P4 4 Row G GND P4 4 Row F UD P4 4 Row E UD P4 4 Row D GND P4 4 Row C UD P4 4 Row B UD P4 4 Row A GND P4 5 Row G UD P4 5 Row F GND P4 5 Row E UD P4 5 Row...

Страница 39: ...Putp01 T PL1N SCN CP 6UOV D P P4 12 Row D GND P4 12 Row C CPutp01 R SCN PL1N CP 6UOV D N P4 12 Row B CPutp01 R SCN PL1N CP 6UOV D P P4 12 Row A GND P4 13 Row G UD P4 13 Row F GND P4 13 Row E CPtp02 DB...

Страница 40: ...er is nominally provided via the VPX backplane In stand alone operation external DC supply can also be provided via header J12 Figure 22 DC supply options 5 15 Headers 5 15 1 J11 FPGA JTAG Figure 23 P...

Страница 41: ...60 DSUM Mar 2022 Version 1 1 5 15 3 J13 Optional SM bus Figure 24 SM bus header 5 15 4 J14 Optional FPGA fan Figure 25 FPGA fan header 5 15 5 J15 Optional PM bus Figure 26 PM bus header 5 16 Switches...

Страница 42: ...ungsgatan 12 SE 411 19 Goteborg Sweden 46 31 7758650 www caes com gaisler 42 GR VPX XCKU060 GR VPX XCKU060 DSUM Mar 2022 Version 1 1 Figure 27 GR716 and FPGA configuration 5 16 2 JP1 SelectMAP Figure...

Страница 43: ...setting 5 16 4 JP3 SpW cross point switch settings Figure 30 SpW cross point switch setting Configuration 1 GR716 connects to backplane FPGA connects to front panel S0 open S1 closed EN0 closed EN 1 c...

Страница 44: ...r 44 GR VPX XCKU060 GR VPX XCKU060 DSUM Mar 2022 Version 1 1 S1 open EN0 open EN1 closed 5 16 5 JP4 JP6 UART and JTAG access Figure 31 SpW cross point switch setting 5 17 LEDs Detailed information for...

Страница 45: ...Cobham Gaisler AB Kungsgatan 12 SE 411 19 Goteborg Sweden 46 31 7758650 www caes com gaisler 45 GR VPX XCKU060 GR VPX XCKU060 DSUM Mar 2022 Version 1 1 6 MECHANICAL DESCRIPTION Figure 32 Top view...

Страница 46: ...VPX XCKU060 GR VPX XCKU060 DSUM Mar 2022 Version 1 1 Figure 33 Top view The design implemented is a 6U high 1 slot 25 4mm wide module for mounting in the controller slot of a 6U rack with a VPX Backp...

Страница 47: ...gure 34 Board dimensions The front panel provides access to the following interfaces described in detail in section 5 2 2 x MDM9S connectors for SPW interfaces 4 x E SATA connectors for SPFI interface...

Страница 48: ...R1 USR2 12 x LED indicators reserved for GR HPCB FMC M2 boards A custom front panel with suitable cut outs and markings is required The figure below represents the front panel PED 00383 DWG which is s...

Страница 49: ...fy that the information in this document is current before using this product The company does not assume any responsibility or liability arising out of the application or use of any product or servic...

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