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Acromag AcroPack AP471 Series, Руководство пользователя

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SERIES AP471 ACROPACK 

 

USER

’S MANUAL 

 

 

 

 

 

 

 

Acromag, Inc. Tel: 248-295-0310  

            - 29 -                                   

http://www.acromag.com  

- 29 - 

www.acromag.com 

 

4.1   Logic/Power Interface 

 

 

The PCIe bus interface logic is embedded within the FPGA.  This logic 
includes support for PCIe commands, including: configuration read/write, 
and memory read/write.  In addition, the PCIe target interface uses a single 
4K base address register.   

A FPGA device provides the control signals required to operate the board.  It 
decodes the selected addresses and control signals. It also returns the 
acknowledgement messages required by the carrier/CPU board per the PCIe 
specification. The program for the FGPA is stored in separate Flash memory 
and loaded upon power-up. 

4.2   I/O Ports 

 

 

The field I/O interface to the carrier board is provided through connector P2 
(refer to Table 2.1). Field I/O points are NONISOLATED. This means that the 
field return and logic common have a direct electrical connection to each 
other. As such, care must be taken to avoid ground loops. Ignoring this effect 
may cause operation errors, and with extreme abuse, possible circuit 
damage.  
 
A Field Programmable Gate Array (FPGA) is used to generate all the logic 
necessary to operate the board. With respect to input acquisition, all 48 
input channels support interrupts and drive the FPGA through buffers. The 
input signal threshold is TTL compatible and includes hysteresis. Further, 
each input channel is connected such that the current status of a given 
output channel can be read back via the corresponding input channel. 
Individual channels may also be masked from writes to the channel when the 
channel is intended for input only to help prevent contention errors. 

Each I/O line includes an integrated 4.7kΩ pull-up resistor to +5V. For inputs, 
the pull-ups provide a low (false=0) input indication if the input is otherwise 
left floating. 

Each I/O line is in the form of an open-drain signal. Thus, data written to any 
channel used as an input must be masked or always false (zero) to avoid 
contention between the output circuitry and an input signal from an external 
device. All 48 I/O lines are placed into the false (high output) state following 
power-up or a system reset. The 4.7kΩ pull-up resistors installed on the 
board provide digital high-drive capability for the output signals.  
  

Содержание AcroPack AP471 Series

Страница 1: ...erutilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In st...

Страница 2: ...O Module USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road Wixom MI 48393 7037 U S A Tel 248 295 0310 Fax 248 624 9234 Copyright 2017 Acromag Inc Printed in the USA Data and specifications are...

Страница 3: ...rdering Information 5 1 3 2 Key Features 5 1 3 3 Key Features PCIe Interface 6 1 4 Signal Interface Products 6 1 5 Software Support 7 Windows 7 VxWorks 7 Linux 7 1 6 References 7 2 0 PREPARATION FOR U...

Страница 4: ...s Read Write 21 Table 3 5 Debounce Duration Register Channels 0 to 15 Channels 16 to 31 and 32 to 47 similar 22 Table 3 6 Debounce Duration Clock Multiplier Selection 22 Debounce Clock Select Register...

Страница 5: ...siderations 31 6 3 1 Operating Temperature 31 6 3 2 Relative Humidity 32 6 3 3 Isolation 32 6 3 4 Vibration and Shock Standards 32 6 3 5 EMC Directives 32 6 4 Reliability Prediction 33 6 5 Digital Inp...

Страница 6: ...ep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag 1 2 1 Trademark Trade Name and Copyright...

Страница 7: ...Key Features The AP471 module provides 48 channels of general purpose digital inputs and outputs Inputs and outputs of this module are CMOS and TTL compatible Each of the I O lines can be used as eith...

Страница 8: ...power down for reliable and safe control Open Drain Outputs Include Pull ups All outputs include 4 7K pull up resistors to 5V Overvoltage Protection Individual I O channels include over voltage clamp...

Страница 9: ...Acromag provides a software product sold separately consisting of VxWorks software This software Model APSW API VXW is composed of VxWorks real time operating system libraries for all AcroPack module...

Страница 10: ...oduct near strong electrostatic electromagnetic magnetic or radioactive fields unless the device is contained within its original manufacturer s packaging Be aware that failure to comply with these gu...

Страница 11: ...ded to prevent a temperature rise above the maximum operating temperature 2 3 Non Isolation Considerations The board is non isolated since there is electrical continuity between the PCIe bus and AcroP...

Страница 12: ...6 9 Field I O 6 12 Reserved isolation 11 Reserved isolation 4 4 7 14 Field I O 7 38 29 8 13 Field I O 8 16 Reserved isolation 15 Reserved isolation 5 5 9 18 Field I O 9 39 30 10 17 Field I O 10 20 Res...

Страница 13: ...Reserved isolation 51 Reserved isolation 14 14 27 54 Field I O 27 48 39 28 53 Field I O 28 56 Reserved isolation 55 Reserved isolation 15 15 29 58 Field I O 29 49 40 30 57 Field I O 30 60 Reserved iso...

Страница 14: ...olation 83 Reserved isolation 22 22 43 86 Field I O 43 56 47 44 85 Field I O 44 88 Reserved isolation 87 Reserved isolation 23 23 45 90 Field I O 45 57 48 46 89 Field I O 46 92 Reserved isolation 91 R...

Страница 15: ...to the mating connector on the carrier board The pin assignments of this connector are standard for all AP modules according to the PCI Express MINI Card Electromechanical Specification REV 1 2 with e...

Страница 16: ...23 PERn0 24 3 3V3 21 GND 22 PERST 19 TDI UIM_C4 1 20 N C W_DISABLE 1 17 TDO UIM_C8 1 18 GND 15 GND 16 N C UIM_VPP 1 13 RECLK 14 N C UIM_RESET 1 11 REFCLK 12 N C UIM_CLK 1 9 GND 10 N C UIM_DATA 1 7 CLK...

Страница 17: ...ration registers A PCIe bus configuration access is used to access an AcroPack s configuration registers When the computer is first powered up the computer s system configuration software scans the PC...

Страница 18: ...board and the Interrupt Register which must be read to determine the interrupt request that goes active on a board interrupt request Table 3 1 Configuration Registers Reg Num D31 D24 D23 D16 D15 D8 D...

Страница 19: ...debounce may also be applied for noise free edge detection of incoming signals Registers are also provided to enable interrupt generation and to generate a software reset Table 3 2 Memory Map Notes 1...

Страница 20: ...ic 1 to enable generation of interrupts from the AP module Setting this bit to logic 0 will disable board interrupts Read Write Bit 0 Disabled 1 Enabled 1 Interrupt Pending Status Bit This bit can be...

Страница 21: ...described by the AcroPack carrier card 31 to 8 Not Used I O Registers Read Write BAR0 0x0000 0008 0x0000 0010 Three registers are provided to control monitor 48 possible I O points Data is read from...

Страница 22: ...Event Polarity Control Registers Read Write BAR0 0x0000 0038 0x0000 0040 A write to these registers controls the polarity of the input sense event for each channel A 1 written to a bit in these regis...

Страница 23: ...for enable via the Interrupt Register All bits are set to 0 following a reset Debounce Control Registers Read Write BAR0 0x0000 0050 0x0000 0058 These registers are used to control whether each indiv...

Страница 24: ...the debounce clock must be re selected to re enable debounce following a reset see below When using I O47 as the debounce clock the effective debounce duration can be calculated by taking the clock p...

Страница 25: ...e not used and will always read as zero XADC Status Control Register Read Write BAR0 0x0000 0070 This read write register will access the XADC register at the address set in the XADC Address Register...

Страница 26: ...16 of the XADC Status Control register at BAR0 plus 0x70H Table 3 7 System Monitor Register Map Address Status Register 0x00 Temperature 0x01 Vccint 0x02 Vccaux 0x20 Maximum Temperature 0x21 Maximum V...

Страница 27: ...s an associated event sense input and debounce logic circuit The event sense inputs are used to sense high to low level or low to high level transitions on digital input lines at CMOS thresholds Inter...

Страница 28: ...e stable for the entire debounce time before it is recognized by the I O or event sense logic Debounce is applied to both inputs and event sense inputs The debounce circuitry can be configured to use...

Страница 29: ...enerated 1 The default debounce duration is 4 s with the default 31 25MHz debounce clock Write 0000 0055H to the Debounce Duration Register to select a 64 s debounce time for channels 0 thru 3 An inco...

Страница 30: ...has been enabled and Interrupt Enable bit 0 1 Note that the state of the inputs on off can be determined by reading the corresponding I O Registers The event sense status can only be determined by re...

Страница 31: ...and with extreme abuse possible circuit damage A Field Programmable Gate Array FPGA is used to generate all the logic necessary to operate the board With respect to input acquisition all 48 input cha...

Страница 32: ...ry Service Procedure CAUTION POWER MUST BE TURNED OFF BEFORE SERVICING BOARDS Before beginning repair be sure that all of the procedures in the Preparation for Use section have been followed Also refe...

Страница 33: ...l Digital I O 40oC to 85oC1 Note 1 Applications requiring operating temperatures of 70 C to 85 C will require purchase of AcroPack Heatsink Accessory AP CC 01 with a minimum airflow of 200LFM For temp...

Страница 34: ...mply with IEC 60068 2 6 10 500Hz 5G 2 Hours axis Vibration Random Operating Designed to comply with IEC 60068 2 64 10 500Hz 5G rms 2 Hours axis Shock Operating Designed to comply with IEC 60068 2 27 3...

Страница 35: ...ut Signal Voltage Range 0 25V to 5 25V DC Input Low Voltage Range 0 8V Max to 0 25V below common ground Input High Voltage Range 2 2V Min to 0 25V above 5V supply Max Input Transition Rise or Fall Tim...

Страница 36: ...com Turn On Time 125ns Typical Turn Off Time 4 7K pull ups 2us Typical 6 7 PCIe Bus Specifications Compatibility Conforms to PCI Express Base Specification Revision 2 1 Line Speed Gen1 2 5Gbps availa...

Страница 37: ...is 20 Bytes with data payload of 4 Bytes for our typical AcroPack For each 4 Byte data sample 24 Bytes are sent 10 4 M samples sec or 41 6 M Bytes sec or 0 332 G bit sec Note 3 For our typical AcroPa...

Страница 38: ...Tel 248 295 0310 36 http www acromag com 36 www acromag com Appendix A AP CC 01 Heatsink Kit Installation This example will show how to install the AP CC 01 Heatsink kit with an APCe7020 carrier AP CC...

Страница 39: ...K USER S MANUAL Acromag Inc Tel 248 295 0310 37 http www acromag com 37 www acromag com 1 Install two standoffs and secure with two screws 2 Install the AcroPack module 3 Install the Heatsink and secu...

Страница 40: ...S AP471 ACROPACK USER S MANUAL Acromag Inc Tel 248 295 0310 38 http www acromag com 38 www acromag com 4 AP CC 01 Installation is complete Note Make sure the thermal pad is making contact with the FPG...

Страница 41: ...Sanitize Power Down Type SRAM SDRAM etc Size User Modifiable Yes No Function Process to Sanitize Non Volatile Memory Does this product contain Non Volatile memory i e Memory of whose contents is reta...

Страница 42: ...marized in the table below Release Date Version EGR DOC Description of Revision 10 AUG 2017 Preliminary ENZ ENZ Preliminary Document Publication 23 OCT 2017 A ENZ MJO Initial Release 15 NOV 2017 B ENZ...

Страница 43: ...uipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentat...

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