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SERIES AP471 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 21 -
http://www.acromag.com
- 21 -
www.acromag.com
Note that no events will be detected until enabled via the Event Enable
Register. Further, interrupts will not be reported to the system unless the
Interrupt enable bit-0 has been configured for enable via the Interrupt
Register. All bits are set to “0” following a reset which means that negative
events will be flagged by default.
Event Pending/Clear Registers (Read/Write)
(BAR0 + 0x0000 0044 –
0x0000 004C)
The Event Pending/Clear Registers reflect the status of the 48 possible
interrupt channels. A “1” bit indicates that an event flag has been set for the
corresponding channel. A channel that does not have events enabled will
never set its event pending flag. A channel’s event can be cleared by writing
a “1” to its bit position in the Event Pending/Clear Register. Bit 0 of each
register corresponds to the lowest numbered I/O point, while Bit 15
corresponds to the highest numbered I/O point.
Note that no events will be detected until enabled via the Event Enable
Register. Further, interrupts will not be reported to the system unless the
Interrupt enable bit-0 has been configured for enable via the Interrupt
Register. All bits are set to “0” following a reset.
Debounce Control Registers (Read/Write)
(BAR0 + 0x0000 0050 –
0x0000 0058)
These registers are used to control whether each individual channel is to be
passed through the debounce logic before being recognized by the circuitry.
A “0” disables the debounce logic for the corresponding channel, and a “1”
enables the debounce logic. Debounce applies to both inputs and event
sense inputs. Bit 0 of each register corresponds to the lowest numbered I/O
point, while Bit 15 corresponds to the highest numbered I/O point.
Furthermore, after enabling the debounce circuitry, wait at least three times
the programmed debounce duration prior to reading the input ports or
event signals to ensure valid data.
Debounce Duration Registers (Read/Write)
(BAR0 + 0x0000 005C –
0x0000 0064)
These registers control the duration required by each input signal before it is
recognized by each individual input. Two bits control the debounce duration
for each channel. If the debounce clock selected is the 31.25MHz internal
system clock (see Debounce Clock Select Register), then the debounce times
are selected as shown below (actual times vary to within minus 25% of
nominal). Alternately, the debounce clock may be input on I/O47 and other
values configured (see Debounce Clock Select Register), but this reduces the
effective number of I/O channels to 47.