Acorn Computers Limited Winchester disk 110, Руководство по обслуживанию

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5.1.2 SCSI connector pinout (PL2 and J4)
Pin no
0V 1 2 DB0
0V 3 4 DB1
0V 5 6 DB2
0V 7 8 DB3
0V 9 10 DB4
0V 11 12 DB5
0V 13 14 DB6
0V 15 16 DB7
0V 17 18 }
0V 19 20 }
0V 21 22 }
0V 23 24 } For future expansion
0V 25 26 }
0V 27 28 }
0V 29 30 }
0V 31 32 }
0V 33 34 +5V to supply test equipment
0V 35 36 BSY
0V 37 38 ACK
0V 39 40 RST
0V 41 42 MSG
0V 43 44 SEL
0V 45 46 C/D
0V 47 48 REQ
0V 49 50 I/O
5.1.3 Bus phases
The bus has several distinct operational phases and cannot be in more than
one of these phases at any given time.
Bus phases occur in a prescribed sequence. The reset condition can interrupt
any phase and is always followed by bus free. Any other phase can also be
followed by the bus free phase.
The prescribed sequence is from bus free to selection to one or more of the
information transfer phases to bus free again.
There are no restrictions on the order of information transfer phases, and a
phase will often follow itself, eg two data phases one after the other.
A typical sequence would be:
bus free
select controller - selection phase
transfer command bytes - command phase
transfer data bytes (if necessary) - data in/out phase
status phase
message phase
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