Acorn Computers Limited Winchester disk 110, Руководство по обслуживанию

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5.3 Winchester Disc Host Adapter
In conjunction with the following description, reference should be made to the
Winchester Disc Host Adapter circuit diagram in the Appendix.
The Winchester Disc Host Adapter is an interface between the SASI/SCSI
interface and the 1MHz expansion bus. It consists of address decoding and
handshake control, buffering of the signals in either direction, and
termination.
5.3.1 Address decoding and handshaking
The Host Adapter decodes 4 locations in the host microcomputer's page FC I/O
space. These four locations are as follows:
Address Read Write
&FC4O
data data (direction determined by R/NW)
&FC41 status ---
&FC42 select
&FC43 enable IRQ
Page FC is decoded in the host microcomputer and this is available to the Host
Adapter as NPGFC (not-page FC). NPGFC is synchronised with 1MHzE by the de-
glitch circuit (half of IC10) and the clean signal is labelled CNPGFC (pin 5,
IC10).
The low order address lines A0 to A7 are buffered through IC5.
IC6, a 3 to 8 line decoder with three enable inputs, decodes the low order
addresses &4O to &43, ie output pin 15 goes low when the low order address is
&40, &41, &42 or &43.
IC7 is another 3 to 8 line decoder which takes the output from IC6 and CNPGFC
and 1MHzE as enable inputs. The 2 least significant address bits A0 and Al are
decoded along with R/NW into the required 5 separate signals shown above.
Y0 (pin 15) is read data (R/NW = 1)
Y4 (pin 11) is write data (R/NW = 0)
Y1 (pin 14) is status
Y6 (pin 9) is select
Y7 (pin 7) is enable IRQ
All these outputs are active-low.
When either of the two data transfer paths is selected (Y0 or Y4) an ACK
signal is generated by clocking a D-type flip-flop (half of IC11). This flip-
flop is cleared direct from the REQ line, and thus the REQ/ACK handshake is
facilitated.
The other half of IC11 facilitates the SEL/BSY handshake. The D-type is
clocked by Y6 to generate select and is cleared by BSY.
When Y7 is selected, the least significant bit on the data bus (D0) is clocked
into a D-type flip-flop (half of IC10). If this value is a 1 then the latch (2
NANDs of IC12) is enabled and an IRQ will be generated at the next falling
edge of REQ. To disable interrupts Y7 is
selected with a 0 on D0. IRQs are enabled only for a very short time (around
10ms) when ensuring a sequential file buffer.
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