Speedster7t GDDR6 User Guide (UG091)
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Chapter - 5: GDDR6 Interface Connectivity
The following sections describe the two interfaces supported by the GDDR6 subsystem to connect to the user
logic hosted in the FPGA fabric, namely the NoC and the beachfront interfaces.
Connectivity to the Peripheral NoC
The Speedster7t FPGA family of devices has a network hierarchy that enables extremely high-speed dataflow
between the FPGA core and the interfaces around the periphery, as well as between logic within the FPGA itself.
This on-chip network hierarchy supports a cross-sectional bidirectional bandwidth of 20 Tbps. It supports a
multitude of interface protocols including GDDR6, DDR4/5, 400G Ethernet, and PCI Express Gen5 data streams,
while greatly simplifying access to memory and high-speed protocols. Achronix's network on chip (NoC) provides
for read/write transactions throughout the device, as well as specialized support for 400G Ethernet streams in
selected columns. For more details, see the
(UG089).
Speedster7t Network on Chip User Guide
The user can connect the GDDR6 subsystems to enable transaction with PCIe or FPGA fabric through the NoC
interface. PCIe can initiate transactions to any GDDR6 channel using NoC. In this case, the PCIe endpoint is the
master with the GDDR6 acting as slave. Similarly, the FPGA master logic can issue a transaction to it's local
Network Access Point (NAP), which carries it to the east or west side of the FPGA core, where it is presented to
the NoC. From then on, the NoC carries data to the appropriate GDDR6 interface. The responses follow the
same path in reverse.
In addition, the NoC provides a connection from the FPGA fabric and IP interfaces to the FPGA configuration unit
(FCU). The FCU receives bitstreams and is used to configure the FPGA fabric as well as the various IP
interfaces on the device. The NoC also provides read and write access to the control and status register (CSR)
space. The CSR space includes control registers and status registers for the IP interfaces.
The NoC connectivity will be the default connection in ACE I/O Designer and is the primary interface expected to
be used. This connection is a 256-bit AXI4 Interface present one per controller per subsystem, running up to 1
GHz generating data rates of 16 Gbps.
AXI4 256b is a 256-bit slave interface which is connected to NoC master AXI.
The AXI4 256b works in single-clock mode, user needs to provide synchronous clock to both read and
write port; it has 256-bit write and read data width.
AXI4 converts AXI transactions to the local bus transactions which connect directly to the MPFE and has
independent command, write and read data FIFO
Supports all burst sizes, types, and lengths including incremental and wrapping bursts.
The figure below shows the I/O diagram of an AXI4-256b Interface.
