A
A
B
B
C
C
D
D
E
E
1
1
2
2
3
3
4
4
All VREF traces should
have 10 mil trace width
Layout Note:
Place near JDIMM1.203,204
Layout Note:
Place near JDIMM1
<Address: SA1:SA0=00>
Channel A
SGA20331E10
330U 2V H1.9
9mohm POLY
M3 support(unpop)
SP07000JN10
DIMM_1 Standard H:4.0mm
1/3 Modify
D_CK_SDATA
D_CK_SCLK
+VREF_CA
+V_DDR_REFA
DDRA_CS0_DIMMA#
SA_ODT0
SA_ODT1
SA_CLK_DDR1
SA_CLK_DDR#1
DDR_A_MA2
DDR_A_MA0
DDR_A_MA4
DDR_A_MA6
DDR_A_MA7
DDR_A_MA11
DDR_A_MA14
DDR_A_BS1
DDR_A_RAS#
DDR_A_MA15
DDRA_CKE1_DIMMA
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D21
DDR_A_D28
DDR_A_D29
DDR_A_DQS0
DDR_A_DQS3
DDR_A_DQS#0
DDR_A_DQS#3
DIMM_DRAMRST#
DDR_A_D23
DDR_A_D31
DDR_A_D13
DDR_A_D20
DDR_A_D30
DDR_A_D14
DDR_A_D15
DDR_A_D12
DDR_A_D22
DDR_A_D36
DDR_A_D37
DDR_A_D45
DDR_A_D46
DDR_A_D52
DDR_A_D53
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_DQS5
DDR_A_DQS7
DDR_A_DQS#5
DDR_A_DQS#7
DDR_A_D63
DDR_A_D39
DDR_A_D54
DDR_A_D38
DDR_A_D47
DDR_A_D44
DDR_A_D32
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_DQS4
DDR_A_DQS6
DDR_A_DQS#4
DDR_A_DQS#6
DDR_A_D48
DDR_A_D33
DDRA_CS1_DIMMA#
DDR_A_MA1
DDR_A_MA3
DDR_A_MA5
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA12
DDR_A_MA13
DDR_A_BS0
DDR_A_BS2
DDR_A_CAS#
DDR_A_WE#
DDRA_CKE0_DIMMA
SA_CLK_DDR0
SA_CLK_DDR#0
DDR_A_D0
DDR_A_D2
DDR_A_D1
DDR_A_D3
DDR_A_D8
DDR_A_D10
DDR_A_D11
DDR_A_D18
DDR_A_D19
DDR_A_D26
DDR_A_D27
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_D17
DDR_A_D9
DDR_A_D16
DDR_A_D25
DDR_A_D24
+3VS
+0.75VS
+0.75VS
+0.75VS
+1.5V
+1.5V
+1.5V
+1.5V
+1.5V
+1.5V
+V_DDR_REFA
+1.5V
SA_DIMM_VREFDQ
<9>
RST_GATE_R
<6,12>
DDRA_CKE0_DIMMA
<6>
DDR_A_BS2
<6>
SA_CLK_DDR0
<6>
SA_CLK_DDR#0
<6>
DDR_A_BS0
<6>
DDR_A_WE#
<6>
DDR_A_CAS#
<6>
DDRA_CS1_DIMMA#
<6>
DDR_A_DQS#[0..7]
<6>
DDR_A_DQS[0..7]
<6>
DDR_A_D[0..63]
<6>
DDR_A_MA[0..15]
<6>
DIMM_DRAMRST#
<6,12>
DDRA_CKE1_DIMMA
<6>
SA_CLK_DDR1
<6>
SA_CLK_DDR#1
<6>
DDR_A_BS1
<6>
DDR_A_RAS#
<6>
DDRA_CS0_DIMMA#
<6>
SA_ODT0
<6>
SA_ODT1
<6>
D_CK_SCLK
<12,14,30>
D_CK_SDATA
<12,14,30>
Title
Size
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
DDRIII DIMMA
Custom
11
45
Friday, April 20, 2012
2011/11/22
2012/11/22
Compal Electronics, Inc.
Q1VZC M/B LA-8941P Schematic
Title
Size
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
DDRIII DIMMA
Custom
11
45
Friday, April 20, 2012
2011/11/22
2012/11/22
Compal Electronics, Inc.
Q1VZC M/B LA-8941P Schematic
Title
Size
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
1.0
DDRIII DIMMA
Custom
11
45
Friday, April 20, 2012
2011/11/22
2012/11/22
Compal Electronics, Inc.
Q1VZC M/B LA-8941P Schematic
C
1
0
6
0
.1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
C
1
2
4
1
U
_
0
4
0
2
_
6
.3
V
6
K
1
2
R
5
9
1
0
K
_
0
4
0
2
_
5
%
1
2
C
1
1
1
1
0
U
_
0
6
0
3
_
6
.3
V
6
M
1
2
R55
0_0402_5%
@
1
2
R56
1K_0402_1%
1
2
C
1
1
5
1
0
U
_
0
6
0
3
_
6
.3
V
6
M
1
2
C
1
2
6
2
.2
U
_
0
6
0
3
_
6
.3
V
6
K
1
2
C
1
0
7
1
U
_
0
4
0
2
_
6
.3
V
6
K
1
2
JDIMM1
TYCO_2-2013022-1
CONN@
VREF_DQ
1
VSS1
2
VSS2
3
DQ4
4
DQ0
5
DQ5
6
DQ1
7
VSS3
8
VSS4
9
DQS#0
10
DM0
11
DQS0
12
VSS5
13
VSS6
14
DQ2
15
DQ6
16
DQ3
17
DQ7
18
VSS7
19
VSS8
20
DQ8
21
DQ12
22
DQ9
23
DQ13
24
VSS9
25
VSS10
26
DQS#1
27
DM1
28
DQS1
29
RESET#
30
VSS11
31
VSS12
32
DQ10
33
DQ14
34
DQ11
35
DQ15
36
VSS13
37
VSS14
38
DQ16
39
DQ20
40
DQ17
41
DQ21
42
VSS15
43
VSS16
44
DQS#2
45
DM2
46
DQS2
47
VSS17
48
VSS18
49
DQ22
50
DQ18
51
DQ23
52
DQ19
53
VSS19
54
VSS20
55
DQ28
56
DQ24
57
DQ29
58
DQ25
59
VSS21
60
VSS22
61
DQS#3
62
DM3
63
DQS3
64
VSS23
65
VSS24
66
DQ26
67
DQ30
68
DQ27
69
DQ31
70
VSS25
71
VSS26
72
A12/BC#
83
A11
84
A9
85
A7
86
VDD5
87
VDD6
88
A8
89
A6
90
CKE0
73
CKE1
74
VDD1
75
VDD2
76
NC1
77
A15
78
BA2
79
A14
80
VDD3
81
VDD4
82
A5
91
A4
92
VDD7
93
VDD8
94
A3
95
A2
96
A1
97
A0
98
VDD9
99
VDD10
100
CK0
101
CK1
102
CK0#
103
CK1#
104
VDD11
105
VDD12
106
A10/AP
107
BA1
108
BA0
109
RAS#
110
VDD13
111
VDD14
112
WE#
113
S0#
114
CAS#
115
ODT0
116
VDD15
117
VDD16
118
A13
119
ODT1
120
S1#
121
NC2
122
VDD17
123
VDD18
124
NCTEST
125
VREF_CA
126
VSS27
127
VSS28
128
DQ32
129
DQ36
130
DQ33
131
DQ37
132
VSS29
133
VSS30
134
DQS#4
135
DM4
136
DQS4
137
VSS31
138
VSS32
139
DQ38
140
DQ34
141
DQ39
142
DQ35
143
VSS33
144
VSS34
145
DQ44
146
DQ40
147
DQ45
148
DQ41
149
VSS35
150
VSS36
151
DQS#5
152
DM5
153
DQS5
154
VSS37
155
VSS38
156
DQ42
157
DQ46
158
DQ43
159
DQ47
160
VSS39
161
VSS40
162
DQ48
163
DQ52
164
DQ49
165
DQ53
166
VSS41
167
VSS42
168
DQS#6
169
DM6
170
DQS6
171
VSS43
172
VSS44
173
DQ54
174
DQ50
175
DQ55
176
DQ51
177
VSS45
178
VSS46
179
DQ60
180
DQ56
181
DQ61
182
DQ57
183
VSS47
184
VSS48
185
DQS#7
186
DM7
187
DQS7
188
VSS49
189
VSS50
190
DQ58
191
DQ62
192
DQ59
193
DQ63
194
VSS51
195
VSS52
196
SA0
197
EVENT#
198
VDDSPD
199
SDA
200
SA1
201
SCL
202
VTT1
203
VTT2
204
G1
205
G2
206
C
1
1
3
1
0
U
_
0
6
0
3
_
6
.3
V
6
M
1
2
C
1
2
2
1
U
_
0
4
0
2
_
6
.3
V
6
K
1
2
C
1
1
9
2
.2
U
_
0
6
0
3
_
6
.3
V
6
K
1
2
C
1
1
6
1
0
U
_
0
6
0
3
_
6
.3
V
6
M
1
2
C
1
2
5
0
.1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
R57
1K_0402_1%
1
2
C
1
0
5
2
.2
U
_
0
6
0
3
_
6
.3
V
6
K
1
2
C
1
1
4
1
0
U
_
0
6
0
3
_
6
.3
V
6
M
1
2
R58
1K_0402_1%
1
2
C
1
0
8
1
U
_
0
4
0
2
_
6
.3
V
6
K
1
2
G
D
S
Q2
BSS138_NL_SOT23-3
@
2
1
3
C
1
1
0
1
U
_
0
4
0
2
_
6
.3
V
6
K
1
2
C
1
2
0
0
.1
U
_
0
4
0
2
_
1
6
V
4
Z
1
2
R54
1K_0402_1%
1
2
C
1
2
1
1
U
_
0
4
0
2
_
6
.3
V
6
K
1
2
R60
10K_0402_5%
1
2
+
C118
330U_D2_2V_Y
1
2
C
1
0
9
1
U
_
0
4
0
2
_
6
.3
V
6
K
1
2
C
1
1
7
1
0
U
_
0
6
0
3
_
6
.3
V
6
M
@
1
2
C
1
2
3
1
U
_
0
4
0
2
_
6
.3
V
6
K
1
2
C
1
1
2
1
0
U
_
0
6
0
3
_
6
.3
V
6
M
1
2
