Acer Altos G520 series, Руководство по обслуживанию

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75 Altos G520
Bootblock Initialization Code Checkpoints
The bootblock initialization code sets up the chipset, memory and other components before system
memory is available. The following table describes the type of checkpoints that may occur during the
bootblock initialization portion of the BIOS:
Checkpoint
Diagnostic LED Decoder
Description G=Green, R=Red, A=Amber
MSB LSB
Before D1
Early chipset initialization is done. Early super I/O initialization is done
including RTC and keyboard controller. NMI is disabled.
D1 R R OFF A
Perform keyboard controller BAT test. Check if waking up from power
management suspend state. Save power-on CPUID value in scratch
CMOS.
D0 R R OFF R
Go to flat mode with 4GB limit and GA20 enabled. Verify the
bootblock checksum.
D2 R R G R
Disable CACHE before memory detection. Execute full memory sizing
module. Verify that flat mode is enabled.
D3 R R G A
If memory sizing module not executed, start memory refresh and do
memory sizing in Bootblock code. Do additional chipset initialization.
Re-enable CACHE. Verify that flat mode is enabled.
D4 R A OFF R
Test base 512KB memory. Adjust policies and cache first 8MB. Set
stack.
D5 R A OFF A
Bootblock code is copied from ROM to lower system memory and
control is given to it. BIOS now executes out of RAM.
D6 R A G R
Both key sequence and OEM specific method is checked to
determine if BIOS recovery is forced. Main BIOS checksum is tested.
If BIOS recovery is necessary, control flows to checkpoint E0. See
Bootblock Recovery Code Checkpoints section of document for more
information.
D7 R A G A
Restore CPUID value back into register. The Bootblock-Runtime
interface module is moved to system memory and control is given to
it. Determine whether to execute serial flash.
D8 A R OFF R
The Runtime module is uncompressed into memory. CPUID
information is stored in memory.
D9 A R OFF A
Store the Uncompressed pointer for future use in PMM. Copying Main
BIOS into memory. Leaves all RAM below 1MB Read-Write including
E000 and F000 shadow areas but closing SMRAM.
DA A R G R
Restore CPUID value back into register. Give control to BIOS POST
(ExecutePOSTKernel). See POST Code Checkpoints section of
document for more information.