b.
At the same time, data bit D7 is also latched in a buffer controller for the associated PPI chip. A high
state disables the buffers and, thus, all four buffers will be put in the tristate mode; i.e. disabled.
c.
Now, if any of the ports are to be set as outputs, you may set the values to the respective port with the
outputs still in the tristate condition. (If all ports are to be set as inputs, this step is not necessary.)
d.
If data bit D7 is low when the control byte is written, ONLY the associated buffer controller is
addressed. If, for example, a control byte of hex 80 has been sent as previously described, and the
data to be output are correct, and it is now desired to open the three ports, then it is necessary to send
a control byte of hex 00 to base a3 to enable the Group 0 buffers. When you do this, the
buffers will be enabled.
Note:
All data bits except D7 must be the same for the two control bytes.
Those buffers will now remain enabled until another control byte with data bit D7 high is sent to base
a3. The buffers for all ports of the group can be tri-stated without changing the PPI
configuration by writing to base a8 with D7 LOW.
Similarly, the Group 1 ports can be enabled/disabled via the control register at base a7. The
following program fragment in C language illustrates the foregoing:
const BASE_ADDRESS 0x300;
outportb(BASE_A3, 0x89); /*This instruction sets the mode to Mode 0, ports A
and B as output, and port C as input. Since bit D7 is
high, the output buffers are set to tristate condition.
See item b. above.*/
outportb(BASE_ADDRESS,0);
outportb(BASE_1,0);
/*These instructions set the initial state of ports A and
B to all zeroes. Port C is not set because it is
configured as an input. See item c. above.*/
outportb(BASE_A3, 0x09); /*Enable the tristate output buffers by using the same
control byte used to configure the PPI, but now set bit
D7 low. See item d. above.*/
Manual 104-DIO-48E, 24E
17
