5-4
IX48 GT3
5.1.2 AC2005 POST Code Definitions
POST
(hex)
Description
Power On Sequence
8.1.
Start power on sequence
8.2.
Enable ATX power supply
8.3.
ATX power supply ready
8.4.
DDR voltage ready
8.5.
Setup PWM for CPU core voltage
8.6.
Assert PWM for CPU core voltage
8.7.
Check CPU core voltage
8.8.
CPU core voltage ready
8.9.
Initial clock generator IC
8.A.
North Bridge chipset voltage ready
8.B.
AGP voltage ready
8.C.
3VDUAL voltage ready
8.D.
VDDA 2.5V voltage ready
8.D.
GMCHVTT voltage ready
8.E.
Check CPU fan speed
8.F.
Assert all power ready
9.0.
Complete µGuru initial process
AWARDBIOS take over booting job
Power Off Sequence
9.1.
Start power off sequence
9.2.
De-Assert all power
9.3.
De-Assert power on
9.4.
De-Assert LDT Bus power
9.5.
De-Assert PWM for CPU core voltage
9.6.
De-Assert CPU core voltage
9.7.
Check CPU core voltage
9.8.
De-Assert ATX power supply
9.9.
Complete power off sequence
Others
C.C.
Either the external “EZ-CCMOS1” switch or the internal “CCMOS1” jumper is not
set to its normal position.
F.0.
Button reset
F.1.
SoftMenu reset
F.2.
Power on sequence timeout
F.3.
Power off sequence timeout
