Abit IT7-MAX2, Руководство пользователя

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BIOS Setup 3-11
3-4. Advanced Chipset Features Setup Menu
The Chipset Features Setup Menu is used to modify the contents of the buffers in the chipset on the
motherboard. Since the parameters of the buffers are closely related to hardware, if the setup is not correct
or is false, the motherboard will become unstable or you will not be able to boot up. If you don’t know the
hardware very well, use default values (i.e. use the LOAD SETUP DEFAULTS option). The only time
you might consider making any changes is if you discover that data is being lost while using your system.
Figure 3-6. Chipset Features Setup Screen
You can use the arrow keys to move between the items. Use
&
,
'
and <
Enter
> key to change the values.
When you have finished setting up the chipset, press < Esc > to go back to the main menu.
NOTE:
The parameters in this screen are for system designers, service personnel, and technically
competent users only. Do not reset these values unless you understand the consequences of your changes.
The first chipset settings deal with CPU access to DRAM. The default timings have been carefully chosen
and should only be altered if data is being lost. Such a scenario might well occur if your system has mixed
speed DRAM chips installed. In such a case, greater delays may be required to preserve the integrity of
the data held in the slower memory chips.
DRAM Timing Selectable:
This item sets the optimal timings for the following four items, depending on the memory module you are
using. The default setting “By SPD” configures these four items by reading the contents in the SPD
(Serial Presence Detect) device. The EEPROM on the memory module stores critical parameter
information about the module, such as memory type, size, speed, voltage interface, and module banks.
#
CAS Latency Time:
This item controls the latency between the DRAM read command and the time that the data becomes
actually available. The options are: 1.5, 2, and 2.5.
#
Act to Precharge Delay:
The options are: 7, 6, and 5.
#
DRAM RAS# to CAS# Delay
This item controls the latency between the DRAM active command and the read/write command. The
options are: 2 and 3.
User’s Manual