48 SBC347A 3U VPX Single Board Computer
Publication No. 500-9300527837-000 Rev. A.0
5.14.2 EEPROM DIP Switch
A PCA9560 device is used to configure the following aspects of board operation:
NOTE
1. This device is write-enabled only when the backplane NVMRO signal (on
) is low.
2. Only default values of the EEPROM DIP switch can be used when booting from the backup BIOS.
The EEPROM DIP switch can be controlled using the BIOS set-up screen.
It is intended only to be used by Abaco software drivers.
LINK
For more details on the DIP switch, see
http://www.nxp.com
.
5.14.3 RAM SPD EEPROM
The SPD EEPROM contains separate Joint Electronics Devices Engineering
Committee (JEDEC) compatible SPD images for each memory controller, which
contain timing and configuration data for the DDR3 RAM. This emulates the case
of two dual inline memory modules (DIMMs) being fitted, and allows the BIOS to
use standard routines to detect and configure the memory during boot-up.
This device is only write-enabled when a jumper is fitted on the
)
or when the appropriate bit in
the EEPROM DIP switch is set (see above), and when the backplane NVMRO
signal (on
) is inactive.
Table 5-12 DIP Switch Options
Output
(Datasheet Name) Function
MUX_A
Reserved
MUX_B
MUX_C
Configuration EEPROM write enable
0 = Writes to configuration EEPROM devices are only enabled when NVMRO
is inactive and when the configuration EEPROM jumper link is fitted (default)
1 = Writes to configuration EEPROM enabled whenever NVMRO is inactive
MUX_D
NVRAM write protect
0 = Writes to NVRAM are enabled whenever NVMRO is inactive (default)
1 = Writes to NVRAM are disabled
MUX_E
SSD write protect
0 = Writes to SSD enabled (default)
1 = Writes to SSD disabled
a
a.
Setting this bit to a ‘1’ may cause instability if an Operating System is installed on the
SSD.
NON_MUXED_OUT
Backplane PCIe REFCLK enable
0 = REFCLK is not driven (default)
1 = Reserved