Aaeon PCM-4330, Инструкция по эксплуатации

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Accessing the silicon disk is performed via 16 kB banks, that are paged into the
address space of the processor. I/O port may be assigned for paging and individual
banks may be designated for paging. Read operations can be performed on bytes,
words or double-words. Special software must be used to write to the silicon disk,
removing the write protection before write operations.
Cache
The i486 family of processors all feature 8 kB on-chip cache and cache controller.
DMA Controller
The DMA controller of the SIS-85C471-AT-Controller offers the ISA functionality
of two 82C37-DMA controllers with seven independent channels.
Interrupt Controller
Two 82C59-compatible interrupt controllers are implemented. They are cascaded
and offer 2 external interrupt channels.
Timer
A 82C54-compatible timer is also included. It comprises three independent chan-
nels which can be programmed in six different modes.
Real-time Clock (RTC)
The RTC is included in the MC146818A-compatible cell of the FDC37C92x-Ultra-
I/O-Controller. It is extended by 128 bytes via two 64 byte CMOS RAM pages in
address space 40h - 7Fh of the RTC.
The RTC manages system time, date, and offers alarm functions. 14 of 192
bytes of internal memory are used to control the clock functions, the remaining 178
bytes of CMOS RAM are used to store BIOS setup information.
Keyboard Controller
The keyboard interface is implemented as a megacell in the SMC FDC37C92x-
Ultra-I/O-Controller. In addition to the serial keyboard port, two ports for system
status and control functions are available.
The keyboard controller manages:
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Keyboard lock
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Color/monochrome toggling
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Address line A20 (1 MB limit)
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Keyboard reset
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Keyboard interrupt request IRQ1
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8