
6240V Mainboard Chapter 3 Award BIOS Setup
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PCI Delay Transaction
This chipset has an embedded 32-bit posted write buffer to
support deadly transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1. The choice : Enabled, disabled space
PCI #2 Access #1 Retry
Enable : PCI #2 will be disconnected if max. retries are
attempted without success. Disable : PCI #2 will be disconnected until access finished.
AGP Mater 1 WS Write
Enable/Disable AGP master one wait state write.
AGP Mater 1 WS Read
Enable/Disable AGP master one wait state read.
Assign IRQ for VGA
When this items is enabled, the system will assign an IRQ for
VGA. If disabled, VGA occupies no IRQ.
Assign IRQ for USB
When this item is enabled, the system will assign an IRQ for
USB. If disabled, USB occupies no IRQ.