FMC150 User Manual
r1.6
FMC150 User Manual
January 2012
www.4dsp.com
- 14 -
5 Controlling the FMC150
Good knowledge of the internal structure and communication protocol of relevant onboard
devices is required for controlling the FMC150. This document only provides guidelines for
programming the devices. For detailed information it is recommended to refer to the
datasheets listed in the related documents section of this document.
5.1 Guidelines for controlling the clock tree
Apart from enabling the onboard reference and VCXO the whole clock tree is controlled by
programming the CDCE72010 device through a serial communication bus. The following
guidelines should be taken into account:
1. The internal reference is enabled by driving REF_EN high. The internal reference
should only be enabled in case internal clock is used and there is no external reference
applied.
2. The onboard VCXO is enabled by default, but can be disabled through the GPIO pins
on the AMC7823 (see section 5.4). This may be useful when using external clock.
3. It is recommended to disable the unused clock outputs.
4. It is recommended to disable PLL functions and VXCO input on the CDCE72010 when
an external sampling clock is applied.
5. In case internal clock is used the PLL functions needs to be enabled. The
recommended phase detector frequency is 160kHz. In case the internal reference is
used the reference divider should be set to 625. The VCO divider is set to 4608.
6. Other phase detector frequencies may be used, but stability of the PLL is not
guaranteed in all cases.
5.2 Guidelines for controlling the ADC
Controlling the ADC enables advanced control of the digitizing process. The ADS62P49 can
be programmed through a serial communication interface to change the output format or using
advanced settings among which gain control, offset correction, and several power down
modes.
1) Low speed mode should be selected for sampling frequencies below 80Msps.
2) External reference should never be enabled.
3) Do not enable CMOS mode when there is LVDS termination on the carrier card.
5.3 Guidelines for controlling the DAC
Controlling the DAC enables advanced control of the conversion process. The DAC3283 can
be programmed through a serial communication interface to change the input format or using
advanced settings among which gain control, offset correction, and several power down
modes.
1) The communication bus can only be used in unidirectional mode; thus using SDIO as
data input and ALARM_SDO as data output.
