FMC150 User Manual
r1.6
FMC150 User Manual
January 2012
www.4dsp.com
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The input impedance is matched to 50
Ω behind the transformers by terminating each node to
the common mode voltage of the ADC. The R-C-R filter near the input of the A/D converter
can be used to improve performance when lower input bandwidth is required. By default this
filter is assembled.
4.5 Analog output channels
The AC coupled output uses wideband RF transformers (TC4-1W). An optional re-construction
filter is available on each DAC output. Refer to Table 2 for the filter characteristics. The filter
can be bypassed on the board with 0
Ω resistors.
Figure 4: Optional DAC re-construction filter.
4.6 External trigger input
The external trigger input is configured as a single ended input. The allowed input range is
ground and 3.3V. The trigger threshold is set to 1.65V
4.7 Clock tree
4.7.1 External clock input
There is one clock input on the front panel that can serve as a sampling clock input or as a
reference clock input (in case the internal clock is desired).
Note: when internal clock is enabled and there is no need for an external reference, it is
highly recommended to leave the external clock input unconnected to prevent
interference with the internal clock.
4.7.2 Architecture
The FMC150 card offers a clock architecture that combines flexibility and high performance.
Components have been chosen in order to minimize jitter and phase noise to reduce
degradation of the data conversion performance. The user may choose to use an external
sampling clock or an internal sampling clock.
TI’s CDCE72010 PLL and clock distribution device is the base of the clock tree. The external
clock input is routed to two RF transformers; one for driving the reference input of the PLL
(SEC_IN) and one for driving the auxiliary clock input (AUXIN). The auxiliary input can be
connected directly to the distribution section of the CDCE72010. The VCO can be powered
down to avoid interference with the external clock.
The VCXO is connected to the VCXO clock input. This clock input connects both to the clock
distribution section and the PLL section. In order to tune the VCXO to a certain frequency a
