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General Automation SPC -16/65, Maintenance Manual

Introducing the General Automation SPC -16/65, a cutting-edge industrial automation device designed to streamline your processes. Unlock its full potential with our comprehensive Maintenance Manual, available for free download at manualshive.com. Empower yourself with this indispensable manual and optimize your operations for enhanced efficiency and productivity.

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Summary of Contents for SPC -16/65

Page 1: ...SPC 16 40 SPC 16 60 SPC 16 80 SPC 16 45 SPC 16 65 SPC 16 85 maintenance manual ...

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Page 3: ...SPC 16 40 SPC 16 45 SPC 1616O SPC 16 65 SPC 16 80 SPC 16 85 maint nance GENERAL AUTOMATION INC 1055 East Street Anaheim California 92805 714 778 4800 1973 1974 General Automation Inc 88A00234A C ...

Page 4: ...88A00234A C REVI1ION Manager Symbol Description Publications Approved Date A Original Issue JC 7 Oc 73 B Added RCSR RCSM tiiP 7 Mar 74 Instructions C Major Revision c lI Aug 74 ...

Page 5: ...emory Option Technical Manual 88A00432A SPC 16 Processor T V Program 6TOOO SPC 16 Memory Test Programs 6T500 6T020 SPC 16 Teletype T V Program 6TIOO SPC 16 Processor and Memory T V Program Manual 88A00184A SPC 16 Teletype T V Program Manual 88A00185A SPC 16 Power Supply Function Test Specification 83S0036A ...

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Page 7: ...d Bus AU 3 3 3 Addend Bus AD 3 3 4 Arithmetic Logic Unit and D Bus 3 3 5 General Purpose Registers Select 3 3 6 General Purpose Registers 3 3 7 P and W Registers 3 3 8 Bit Select Logic 3 3 9 Relative Time Clock RTC 3 3 10 Operations Monitor Alarm O 3 3 11 Q and R Registers 3 4 Master Interconnect Board MIB 3 5 3 4 1 SPC 16 40 60 80 MIB Connectors 3 4 2 SPC 16 45 65 85 Main MIB Connectors 3 4 3 SPC...

Page 8: ... nterrup lmlng Register Ad1ress Bus Augend Addefd Selects Register Set s Priority Interrupt Expander MIB Interfa e Plugs and I nput Out ut Board MIO Memory Data M Register Memory Addr ss L Register I O Drivers Receivers and Termination Memory Stacf Select System Rese and Memory Guard Relays Serial Te1 type Controller i t f 1 g Ptica1 Computers Board MEM DAT j FLOW 4 1 Data Flow Organizatir n 4 1 1...

Page 9: ...nditional JMP Logic 6 4 Memory Reference with Indexing Instructions HRX 6 4 1 Load Register LDR 6 4 2 Stor Register STR 6 4 3 Compare Memory with Register CMR 6 4 4 Bit Byte Mode Addressing 6 4 5 Load Byte LDBY 6 4 6 Store Byte STBY 6 4 7 Set Bit SBIT 6 4 8 Reset Bit RBIT 6 4 9 Test Bit TBIT 6 4 10 Increment Memory INCM 6 4 11 Decrement Memory DECM 6 4 12 Load All Registers and Status LARS 6 4 13 ...

Page 10: ...s 7 2 2 Memory Cycl es Decoder and Drive S itches Regulator and Curred t Source 7 4 1 Regulator 1 7 4 2 Current So rces 7 4 3 Quiescent onditions Current Source Off 7 4 4 Current Tu n On 7 4 5 Current Tu n Off 7 4 6 Memory Gua d Sense Amplifier and Inhibit Drivers T ming and Control Memory Logic Signal Mnemonics SPC 16 POWER SUPPLY 8 1 Power Fail Detect Ci rcuit PREVENTIVE MAINTENANCE PROqEDURES 9...

Page 11: ... s Signal Mnemonic Definition Component Interchangeahility Parts List Computer Mainframe Assembly SPC 16 Console SPC 16 40 60 80 Typical System SPC 16 45 65 85 System with Fully Expanded Memory Installation Drawing SPC 16 40 60 80 Model 1640 or 60 or 80 SPC 16 40 60 80 Internal Board Arrangement Installation Drawing SPC 16 45 65 85 with 0 32K Memory Capability Installation Drawing SPC 16 45 65 85 ...

Page 12: ...ruction Summary exadecimal Coding LDA Instruction Sequence Ch1 art STA Instruction Sequence Ch1 art JSR Instruction Sequence Ch1 art JMP Instruction Sequence Ch1 art LDR Instruction Sequence Chart STR Instruction Sequence Chlart CMR Instruction Sequence c art LDBY Instruction Sequence Chart STgy Instruction Sequence Chart SBIT Instruction Sequence Chart RBIT Instruction Sequence Chart TBIT Instruc...

Page 13: ...Switch Schematic Regulator Schematic X Current Source Schematic Sense Amplifier and Inhibit Driver Schematic Memory Timing Diagram Timing Diagram of Power Fail Automatic Restart Removing Fans Pin Assignments DC Power Input Connector Power Supply Adjustment Potentiometers Timing Diagram WAIT Memory Allocation for Base Relative Indirect LDR Instruction with Indexing Removing Console Board Removing M...

Page 14: ...Component Compatibility Component Compatibility Component Compatibility Component Compatibility Component Compatibility Component Compatibility Computer Mainframe Assembly Computer Mainframe Assembly Computer Mainframe Assembly Computer Mainframe Assembly Computer Mainframe Assembly Computer Mainframe Assembly MIB Memory Compatibility Chart I viii Page 6 6 6 7 7 15 9 4 10 11 B 1 B 2 B 3 B 4 B 5 B ...

Page 15: ... drawings intended to give the reader a basic orientation as to the physical layout of the computer o Section 3 describes the functional organization of the SPC 16 Central Proces sing Uni t o Section 4 describes data flow within the computer o Section 5 describes the basic timing signals in the SPC 16 processor o Section 6 presents sequence diagrams for the SPC 16 instruction set o Section 7 descr...

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Page 17: ...els the I O logic is housed in the computer mainframe This configuration provides eight card slots for peripheral controller boards four card slots for memory logic boards and four card slots for processor logic boards A memory slot will accept any of the following memory modules eA Read Write Memory module with 4K 8K or 16K word capacity e If 4K 8K and or 16K modules are intermixed the 4K must be...

Page 18: ...ory boards The external I O bJs is cabled to the external I O enclosure which contains the controllers The extJrnal I O enclosure has 18 card slots avail I able for peripheral controller cards an one slot reserved for a cable interface card MIB c 0 __ o c c c c c o 0 c o c o D 0 0 c c c 0 0 0 C 0 0 O a 0 SPC 16 FRONT VIEW EXTERNAL I O BUS 11111111 11 11 EXTERNAL I O ENCLOSURE PERIPHERAL DEVICE PER...

Page 19: ...048 and 4096 word increments o Read Write Memory module available in 4096 and 8192 word sizes o Read Wri e Memory module may include 32 or 64 word ROM o Lithium ferrite core stacks with wide temperature tolerance used on Read Write Memory each stack has an independent current regulator o Metal oxide semiconductor rcs used on _ _ _Rea onlY Memory boards I Address ing o Single and double word addres...

Page 20: ...are 11 Register operate literal and compare 11 Register change 16 Shift 0 to 16 bits 4 Control 9 Input Output for up to 64 devices single word instruction addressing 6 Hardware Multiply and Divide optional 2 o All instructions may be stored in either Read Write or Read Only Memory modules o Execution times vary with the complexity of the instruction and are a multiple o o o 1 4 of memory cycle tim...

Page 21: ...s of memory by peripheral unites using o o o o a cycle stealing technique Transfer rates for the three model pairs are SPC 16 40 45 SPC 16 60 65 SPC 16 80 85 694 4 KHz 1041 6 KHz 1250 0 KHz Sixteen DMA channels are provided as standard The controller physically nearest to the CPU has priority Six een memory locations are dedi ca ted to the standard DMA channels Power Fail Hemory protection standar...

Page 22: ... Console lock out switch key operated Operations monitor alarm Console interrupt General Dimensions SPC 16 40 60 80 and 45 65 85 without M emory Expansion options Height 10 5 inches 26 7 centimeters Width 19 0 inches 48 3 centimeters Depth 21 6 inches 54 9 centimeters Weight max approx 55 lbs 25 kilograms o SPC 16 45 65 85 with 64K M emor y Expansion 1 option Height 12 2 inches 31 0 centimeter s W...

Page 23: ...e phase 220 vac 10 47 to 63 HZ single phase 700 watts 4K core add 40 watts per additional 4K DC Current Requirements See Tables 1 2 and 1 3 for current requirements for all boards in system Site Preparation No special wiring subflooring air conditioning or other site preparation is required ...

Page 24: ...MIO Arithmetic Macro CPU Boards Timing lO OOA O 60A Console MIB Expanded MIB MLD Board SPC 4l6 45 65 85 only O 25A O 12A 4K Memory Boar Operating O 92A 1 70A 1 25A 6 00A 8K Memory Boar d O 90A 1 40A 1 40A 6 00A 4K Memory Boarq _ O 68A O 15A O 30A 8K Memory Board Idle O 80A O 20A O 40A 1 8 ...

Page 25: ...1 75A 3317 6200 CR 1 75A 3318 6200 CR 1 75A 3314 6200 CPo 1 1 15A 3321 6200 PTR 1 50A 3322 6200 PTP 1 50A 3323 6200 PTR PTP 1 97A 3325 6200 PTR PTP 1 97A I 3331 6200 MTU 3 3 76A 3332 6200 MTU 3 3 76A 3333 6200 MTU 3 3 76A 3334 6200 MTU 3 3 89A 3335 6200 MTU 3 3 89A 3336 6200 MTU 3 3 89A 3341 6200 DISK 3 4 46A 3342 6200 HPTSD 2 2 35A 3343 6200 DISK 3 4 46A 3346 6200 DISK 2 2 81A 3347 6200 DISK 2 2 ...

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Page 27: ...ssor can be ordered in three basic versions o Model 1645 or 65 or 85 1100 is supplied with one 4K memory board and can accommodate up to three additional 4K memory boards without purchasing additional options Memory can be expanded to accommodate four additional 4K memory boards by installing the optional Internal Memory Expansion Board 1645 or 65 or 85 0097 o Model 1645 or 65 or 85 1200 is suppli...

Page 28: ...o l o o z o 01 l o Z G o SPC 16 40 60 80 rawl ng 1359 2 1 Installation r 1159 1259 or _ Figure or 60 or 0 _ Model 1640 22 a ...

Page 29: ...ers are based on access priority Peripheral unit associated with pontroller Board 1 has highest access priority etc 2 Usi g 8K memory boards First Memory Board provides 8K of memory Adding Second Memory Board increase memory to 16K adding Third Memory Board increases memory to 24K all four memory boards provide 32K of memory 3 Using 4K memory boards all four memory boards provide 16K 4 Controller ...

Page 30: ...DIRECT ION 5 800 1 251 5 bO I 25i 1 _ G 2 f47 OJl GROUND STRIP r 10 44 l 16 32 1 t AEMQl1 y E PA SION TyP CHASSIS AND LOGIC GNu Q f AVAILABLE 10 25 A 3 00 j 0 16K BASIC E ORY ill TYP I l g g 1 2 675 030 t r Q lcPu L_ __ L L 84 f C J I J I 4_00 t I 1 5 300 060 I 19 00 1 020 06 0 I TvP 5 300 060 1 A C FAN POwER CORD TvP DC PC R oNPuT CONNECTOR l 3MAX ALL OWAI3L E CONNECTS TO RE OT E POWER SUPPLY TTY...

Page 31: ...Z Xl Xl o o o w G z o o 1 0 C 0 al i Figure 2 4 Installation Drawing SPC 16 45 65 85 With Expanded 32 64K Memory Option Model 1645 or 65 or 85 1200 or 1300 with 0095 Memory Expansion Chassis Installed 2 5 ...

Page 32: ...R BOARD THIRD MEMORY OARD FOURTH MEMOR BOARD I MEMORY INPUfOUTPUT BOAR 0 MACROCONTRO BOARD I TIMING CONTRO l BOARD t t TE 1 Using 8K memory boards irst Memory Board provides 8K of memory Adding Sec9nd Memory Board increases memory to 16K etc All r ight boards provide 64K 2 Using 4K memory boards 11 8 memory boards provide 32K Figure 2 5 SPC 16 45 65 5 Internal Board Arrangement Expanded Memory Opt...

Page 33: ...low a flow of information within the computer that is both efficient and uncomplicated The Augend and Addend buses are the paths by which all data enters the Arithmetic Logic Unit The Data bus is the path by which data is transferred from the Arithmetic Logic Unit to other elements of the system ARITHMETIC LOGIC UNIT The Arithmetic Logic Unit is the central element of the computer it is used in ex...

Page 34: ... J r r MEMORY W R SHFT I IO L I L ____ l L _ J ARITHMETIC L_ I AND t LOGIC f r UNIT r WREG P J i f Z I L REG L_ I L_ r I R SWAP S REG r L _ _ _ _ Q R SHFT I H K REG l _____ DATf BUS QREG I GENERAL R REG j PURPOSE REGISTERS A REG A X X Y Y FOREGROUND Z Z BACKGROUND MODE MODE REGISTERS B B REGISTERS C C 0 I 0 E I E r Figure 3 1 Internal Ar angement of the CPU 3 2 ...

Page 35: ...s A register As A register Contains the base address for base relative addres sing as pre index Otherwise used as A register During subro tine or interrupt execution con tains return address and Interrupt Status Enable Control Otherwise used as A register With the foreground background option eight additional general purpose registers may be used Only one set of registers is active at a given time...

Page 36: ...r the R Register or both Instructions are pr ovided to perform the f l llowing operations on any of the eight general purpose registers Load regis ter from memory word 0 Store register in memory word or Arithmetic and logical operations ADD SUBtract OR AND eXclusive of one to another byte byte between any two registers OR XOR transfer the contents Arithmetic and logical operations between any regi...

Page 37: ...ous arithmetic operation An instruction is provided to add the contents of the Link to any general purpose register Thus a carry out of bit 15 from one register containing the right half of a number may be added to another register containing the left half of he num ber allowing the contents of the two registers to be treated as a single number 2 Shift During the execution of a shift instruction t...

Page 38: ... bit of the P Register conta ns the Interrupt System Enable ISEr indicator When roading the P Register vi the computer console the ISE bit is not affected 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 The Program Counter normally contains the rddress of the next instruction to be executed Its contents bits 0 14 are tra sferred to the L Register Memory Loca tion Register following the execution of the curren...

Page 39: ...w order l2 bits indi cate the address within this selected portion The L Register is always loaded from the Data Bus M REGISTER The M Register 16 bits is the memory buffer register It receives all data read from and contains all data written into the computer s memory The M Register can be loaded from the Data bus It can be selected onto the Addend bus into the I Register or through the I O Driver...

Page 40: ...bus and may be selr cted onto the Augend bus A non addressa ble r e g ister labeled W R SII T in Figur e 3 1 is the J Registe r wit h bit s shifted one ppsition to the right H SHFT may also b e ga ted onto the Augen d bus used for ha rdwa re mult i p ly onl K REGISTER he contents of the K Register 16 bits a e continuously displayed on the computer console s Register Display Indicators An nstructio...

Page 41: ...ocations in Figure 3 2 The console switches and indicators are described in Appendix D The basic SPC 16 instruction set may be executed with this board removed OPERATING INDICATORS DIGITAL TO ANALOG CONVERTER Cf l DISPLAY REGISTER K a w u u a w z DATA ENTRY SENSE SWITCHES CONSOLE co INTERRUPT REGISTER DATA ENTRY CONTROL KEY SWITCHES SWITCHES LOCK COMPON ENT SI DE Figure 3 2 Console Board Functiona...

Page 42: ...ind the console cover is a maintenance AVE I switch which operates independent of the RUN IDLE switch for continuous execption of a stngle instruction in the run mode The SAVE I switch on the console ope ates only in the idle mode 3 2 5 Register Select Switches Register select switches 1 2 and 4 the S ATUS select P and select I switches are all 2 position switches The switches rre wired in a prior...

Page 43: ... metic Board Assembly number 3lD01333A are shown in their approximate locations in Figure 3 3 W P REGISTERS J J l a UJ RTC MACRO u AUGEND t MICRO LL BUS a SELECTS UJ r MACRO z MICRO GENERAL co SETS PURPOSE Q R REGISTERS REGISTERS SELECT BIT SELECT SET BIT SELECT N J ADDEND J l BUS a UJ GENERAL PURPOSE u OMA t REGISTERS FOREGROUND LL a AND BACKGROUND UJ t co MACRO MICRO MACRO MICRO ARITHMETIC LOGIC...

Page 44: ... RAB2 decode one of eight registers The state of the f oreground flip flop det rmines vhich group of eight registers either foreground or background is sele ted 3 3 6 General Purpose Registers The 16 general purpose registers are A A X X Y Y Z Z B B C C D D E and E The primed registers indica e background registers and the unprimed registers indicate foreground registers 3 3 7 P and WRegisters Bit...

Page 45: ...set and the RTC and OMA counters are initialized to time out in 100 machine cycles One hundred machine cycles are available after power fail until the CPU is forced into a stall 3 3 11 Q and R Registers Any of the general purpose registers can be inputs to either the Q or R register The outputs of the R register go to either the augend or the addend bus The out puts of the Q register go to the aug...

Page 46: ...Y EXP CONNS MEM EXP CONN 0 I 5 Z Z Oa Z z 1EMORY CONNECTORS a I O 1 0 LOWER 9C JU I U OC POWER CONN CONSOLE l U CONNECTORS CONNS COMPoNENT SIDE MA N MIB I MEMORY LOCATION DISPLAY CONNECTORS EXPANDED MEMORY l pPER EXPANDED MEMORY CONTROL LOGIC fMORY CONTROL LOGIC I ONNECTORS MEM EXP CONNS MEM EXP CONN COMP f l NENT SI DE EXPAND D MEMORY MJB Figure 3 5 SPC 16 45 65 85 Master In erconnect Boards Func...

Page 47: ...ors and their respective jack designations on the SPC 16 45 65 85 Main M IB are as follows Board Connector Jack Designation s Console Jl J2 Hemory J3 J4 J5 J6 Timing J7 J8 Macro J9 JlO Arithmetic Jll J12 MIO J13 J14 Ground J15 TTY J16 DC Power J17 Memory Expansion J18 J2l 3 4 3 SPC 16 45 65 85 Expanded Memory MIB Connecto r s The connectors and their respective jack designations on the SPC 16 45 6...

Page 48: ...functional sections of tHe 1acro Control Board Assembly number 31D01331A are shown in their approximate lccations in Figure 3 6 I C I w C AUGEND ADDEND a SELECTS J a w a w I w I C U Z 3 w u 0 a a w U I I u I co C COMBINATION TIMING r INSTRUCTION ALU N REGISTER FUNCTION BUS J a w U INDICATORS u INSTRUCTION a w REGISTER I DECODE co COMPONE JTSIDE Figure 3 6 Macro Control Boa d Functional Arrangement...

Page 49: ...he augend addend select functions shown in Figure 4 1 are generated on the Macro Control Board They are SMMS6 SM04 SM58 SM9 SMX8 SHX9 SBITR SBITL SZPOL SS SRLL SRRR SHFW SIO SQLL SQRR SRRL SRLR SW SP SI and SHFQ are generated on the Timing Control Board These signals are defined in Section 4 3 5 5 Register Set Functions The I and K register set functions STI and STK are found on the lacro Control ...

Page 50: ...PT CLOCK U EXPANDER MC u a TIMING w f I SEQUENCE CONTROL REGISTER SETS DO N CLOCK c DOC J z TIMING J 0 a w U c AUGEND REGISTER SEQUENCE u coz a ADDEND ADDRESS TIMING w o f SELECTS BUS Uf co DO TIMING COM ONENT SIDE Figure 3 7 Ti ming Cont 01 Board Functional Arrangement 3 6 1 t1aster Clock The crystal controlled master clock pulses are 90 60 and 50 ns respectively from leading edge to leading edge...

Page 51: ...ry Timi ng The memory start enable signal MSE is generated at either D02 or D04 time The memory timing MTIM flip flop the read cycle READ signal the write cycle O 1RIT signal inhibit INHT and memory start clock MSTC are all generated on this board Also the clear M register CLRML CLRMR signals are generated here 3 6 3 Programmed Input Output PIO DMA Interrupt Timing The following I O and DMA timing...

Page 52: ... Priority Interrupt Expander The six holding fltp flops for the interru t request signals are active at all times except at interrupt acknowledge IACK tile During lACK no level changes are allowed while the Branch Vector address is decoded The second group of six flip flops are the mask register used for the d sarming The inputs to the second group of flip flops come from the M register during a s...

Page 53: ...Figure 3 8 INTERRUPT I O RECEIVERS I O CONTROL C l t U J UJ l MEM a l 0 UJ SELECT UJ C UJ lC U la oUJ u u L REGISTER a a l I 1 0 UJ 1 ii z J C I a l UJoo Z UJ c uu a C a 0 co I UJ I O SERIAL M REGISTER DRIVERS CONTROLLER COMPONENT SI DE Figure 3 8 Memory and Input Output Board Functional Arrangement 3 7 1 Memory Data M Register The 16 bit M register inputs come from the data bus and memory The out...

Page 54: ...I SYRT and SYRT I through normally closed contacts to ground When power reactes an unsafe condition via PFD the relay is de energized resulting in a SYRT bondition While power is in the safe range the relay is energized yielding a false SYRT signal The memory guard relay provides 15V to the memory through normally open contacts While power is safe the contacts are c osed and 15V is presented to me...

Page 55: ...tablish the TTY interrupt TTYI and the teletype test line true condition This indicates to the processor that it is time to place a new data word in the shift register or to get the data that has been input 3 7 7 Serial Controller Optical Couplers The serial controller optical couplers Z9HA Z9HB form the interface between the controller and the teletype The couplers are used to electrically and ph...

Page 56: ...Y CURRENT SOURCE MEMORY DATA RCVRS INHIBIT J RIVERS OU PUT GA ES SHADED AREA INDICATES 4KXI6 PLANAR ARRAY MEMORY DATA RCVRS X CURRENT SOURCE Figure 3 9 Low Profil e Pi a ar Array 4K Memory Board 3 24 ...

Page 57: ...Y CURRENT SOURCE MEMORY DATA RCVRS INHIBIT DRIVERS OUTPUT GATES SHADED AREA INDICATES 8KXIG PLANAH J R HA Y MEMORY DATA RCVF S x Figure 3 10 Low Profile Planar Array 8K Memory Board 3 25 ...

Page 58: ...Figure 3 11 Planar Array 3 26 EA INDICATES SHADED A AR ARRAY 16K XI6 PLA Board 16K Memory ...

Page 59: ...ocks shown in Figure 4 1 4 1 1 Arithmetic Logic Unit ALU The Arithmetic Logic Unit can act as a l6 bit binary adder or as a logical _function generator depending upon the level of its mode control input FINH Hith FINH low the ALU performs arithmetic operations on the Augend Bus and the Addend Bus with FINH high the ALU performs logical operations on these busses The particular operation performed ...

Page 60: ... 1 j H 0 j i3 i I 1 1 1 I T I I T v I I l l I I T I I x v V 1 I I v I v lr g IIIII L n r r LJ L iL Figure 4 1 SPC 16 Block Diagram I 4 L l lliJ ...

Page 61: ...F AB minus I L L H L F AB minus 1 L L H H F minus I 2 s complement L H L L F A plus A B L H L H F AB plus A B L H H L F A minus B minus 1 L H H H F A B H L L L F A plus A B H L L H F A plus B H L H L F AB plus A B H L H H F A B H H L L F A plus A H H L H F AB plus A H H H L F AB plus A H H H H F A i Hith mode control FINH and FeIN lmv 4 3 ...

Page 62: ...ow Levels Active L L L L F A L L L H F AB L L H L F A B L L H H F Logical 1 L H L L F A B L H L H F B L H H L F AC B L H H H F A B H L L L F AB H L L H F ACBB H L H L F B H L H H F A B H H L L F Logical 0 H H L H F AB H H H L F AB H H H H F A Hith mode control FINH high FeIN irrelevant ...

Page 63: ...nd Bus SQLL The Select Q register Left to Left logic gates bits 8 15 of the Q register to bits 3 15 of the Augend Bus SQRR The Select Q register Right to Right logic gates bits a 7 of the Q register to bits a 7 of the Augend Bus SRRL The Select R register Right to Left logic gates bits a 7 of the R register to bits 8 15 of the Augend Bus SRLR The Select R register Left to Right logic gates bits 8 ...

Page 64: ...ta Register and Extend bit 8 logic gates bit 8 of the M register to bits 9 15 of the Addend Bus This is referred to as extended dis placement Sl 9 The Select Memory Data Register and Extend bit 9 logic gates bit 9 of the s Sl i r st el i St e C da ne n e S Bus I RBIT The Reset Bit logic forces a logical zero into the bit selected on the select Indicators logic gates l lhe following indicators to t...

Page 65: ...ckground indicator The following paragraphs describe the selects associated with the Data Bus ZPOLS This select gates the Data Bus bits listed below to the specified indicators Indicator Data Bus Bit Foreground DB08 Zero DB07 Plus DB06 Overflow DBOs Link DB04 Also the ZPOLS logic gates bits 0 3 of the Data Bus to bits 0 3 of the Shift Counter STU The Set W logic gates bits 0 15 of the Data Bus to ...

Page 66: ...1 1 1 o o 1 1 o o 1 1 o o 1 1 o o J 1 o 1 o o 1 o 1 o 1 o J o 1 o 1 o 1 o 1 o 1 o 1 J J 1 1 1 1 o o 1 o o 1 1 o o o o o o o o o o 1 1 o 1 1 1 o o o o o 1 o 1 o 1 o 1 o o o o 1 1 1 1 1 1 1 1 1 0 o Link o 0 o 0 1 1 1 1 1 0 o 0 o 0 o 0 1 1 1 b 1 1 1 ALU Function A plus 13 A minus 13 minus 1 A A B A minus 13 A and 13 A Xor B A plus 13 A plus B A plus B A X or 13 A or 13 A plus 13 plus 1 A or B When Us...

Page 67: ...ground or background is dependent upon the state of the foreground background mode control flip flop FRGllD If the foreground background flip flop is set the foreground registers are selected if the flip flop is reset the background registers are selected The 16 general purpose registers and their associqted addressing and selection logic are implemented in matrix fashion with sixteen l6 bit scrat...

Page 68: ... RAB1 E Z E Z S1 JIll YS3B Y SEL ECTION JIll D Y D Y LOGIC YS2B RABO C X C X SO JlI YS1 B B A B A I W1 l WO I WRITE SELECTION I IWRITE SELECTI ON I LOGIC LO GIC fi r 7 DATA US I TYPICAL FOR EACH Bl if Q REGISTER I I R REGISTE R 1 Figure 4 2 Operational Regist er Organizatio n 4 10 ...

Page 69: ...ts on each of the 16 scratch pad memory integrated circuit chips If the instruction being executed requires a read from the specified register activation of the selected X and Y lines selects the contents of one bit of each of the 16 scratch pad chips which is then gated into the associated bit position of either the Q or R register If the instruction being executed requires a load into a register...

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Page 71: ...progress Each hardware step of this micropro gram can be labeled in the following general form Sa DOb where a 1 2 3 4 5 6 7 8 or 9 and b 1 2 3 or 4 S stands for Sequence State of the SPC 16 There are 9 possible sequen e states Sl through 59 Each sequence state usually t kes 1 memory cycle DO stands for DO Time To properly time the execution of each sequence state each computer memory cycle has bee...

Page 72: ...uction and end sift right count not complete b Extended processor option flip f c Multiply iristruction and sequenc state 9 d Non memory reference instruction instruction fetched from ROM no power fail interrupt PFIR RUN mode op rational and no interrupt request If none of these conditions are present then the D04 time is entered 5 1 3 Sequence States In defining the Sequence States the de igners ...

Page 73: ...OC12 J o 001 J 002 180 120 100 270 180 150r l 360 240 I 200 360 240 2 EJ r l 720 480 r l r L L 003 ___________________________4 O 0Ir _____ 004 MSTC MEMORY STRB 002 003 MSTC MEMORY STRB 00C1 00C2 SAME AS ABOVE 1080 720 _________________ 6_0 fI L 1 ROM MEMORY CYCLE FOR NON MEMORY REF INSTRUCTIONS 720 NS 480 NS 400 NS L Figure 5 1 Basic Timing 5 3 ...

Page 74: ...1 10 70 10 70 I 00C1 10 70 I 10 70 00C2 70 130l 00C2 70 130 00C3 130 190 DOc 13q 190 00C4 190 10 00C4 190 10 00C12 10 130 10 00C12 10 130 10 D010R310 r DO 1 OR 3 10 DO lOR 3 10 DO 1 OR 3 10 DO 2 OR 4 15 20 DO 2 OR 4 20 15 Figure 5 2 Basic T iming of Professor DOC and DO Worst Case SL4 ...

Page 75: ...001 cO CD 11 W 0 1 11 0 I I 1 11 J co 0 002 003 L XPOF y MPY S9 OMA 004 NOT ENTERING YES Sl 001 RUN WAIT ...

Page 76: ...ccesses second word f instruction D02 P l ISE P D03 M index if any W D04 If base relative D W 1 W L S3 Indirect addressing state MR M DOl D02 Memory is accessed pr ducing indirect address D03 Indirect address index if any W D04 W L S4 Used only by LARS and SARS S5 DOl Memory cycle initiated for l r ading or storing register D02 Register M Db3 W is incremented Re ister count is incremented D04 W L ...

Page 77: ...3001 INDIRECT NO LARS SARS S4001 JMP ES S1001 JSR NO S5001 INDIRECT N ES ESS4001 tSARS NO S5001 R f ES ESS4001 SARS NO STATUS S2001 S5001 REG rES S5001 CTR NO RSC 01 continued on 8 S40 e on next pag 4 Sequence Figure 5 Flowchart State Timing 5 7 ...

Page 78: ...STATE NINE S9 ENDSR INTERRUPT REQUEST DMA CYCLE GEN ROL MPY DVD WAIT ES S7D01 NO S1D01 DMA CYCLE REQUEST DMA CYCLE REQUEST ENDSR Figure 5 cant d l 8 MPY DIV YES S9D02 XPOF A INST FETCHED FROM PFIR RUN ROM ITCRHSE S1D01 S8D01 RETURN TO ACTIVE SEQUENCE STATE 004 ST ES S8D04 NO MPY NO S9D01 ...

Page 79: ...ly Divide instructions It allows the computer to perform the necessary number of add and shift operations Algorithm for these instructions is given in Section 3 10 of SPC 16 40 Reference Manual Timing flowcharts for eight of the sequence states S6 is omitted are shown in Figure 5 4 The sequence flip flops are clocked by the sequence advance clock A SACKA and sequence advance clock B SACKB The SACK...

Page 80: ...2 OPERATIONS TIMING 5 2 1 Memory Timing A memory start clock signal is issue at the beginning of each instruction cycle If Read Only Memory is being accesse and the instruction is non memory reference the next memory start clock will be ssued at the end of D02 If read write memory or ROM with memory reference is be ng accessed the next memory start clock will be issued at the end of D04 The timing...

Page 81: ... 60 50 001 180 120 100 270 180 150 360 240 200 90 60 50 002 180 120 100 E J DOC2 tA 270 180 150 720 480 40 003 Ld DOC2 Ld DOC3 ILl IJ DOC3 fLl STl OR MSTC1 INVALID X V SWITCH INHT I DOC12 YIEN YI 135 NS I Ed DOC4 ILl READ WRIT 235 NS Y CURRENT ENABLE 1 I SA VA fZ ClM MSTC2 1 MTIM FOR INHT yzJ SETM V I I OOD I ...

Page 82: ... Memory Access Arithmetid Logic Control I O The SPC 16 direct memory access port ffers optional control lines that permit the I O unit to perform arithmetic and lo iC operations between external data and t he contents of memory Each operation is performed in a single memory cycle time 5 2 4 Serial I O Interface The serial I O provides the interface between the serial controller and the tele type T...

Page 83: ...olled by automatic and programmed control of the Interrupt System Enable elSE flip flop Also each level may be individually masked for optimum control of the system The interrupt system is described in Section 2 of the SPC 16 40 System Reference manual 88A00243A 5 2 6 Power Fail Automatic Restart Refer to Figure 5 8 for a diagram of the auto restart timing Power Fail Auto Restart is explained in d...

Page 84: ... V M N S 0 N I l I l _ L L __ t 1 l T T T W l u r o Figure 5 8 SPC 16 Au 0 Restart Timing Run Mode 5 14 T f I W U 0 f a u Cl J I ill ...

Page 85: ...ght Arithmetic Enabl d SRCCE Shift Right Circular or Shift Right Circular Link Enable e CTRLE Control Instruction Enable f RCSE Register Change Source Instruction Class Enable g RCDE Register Change Destination Instruction Class Enable h RCOE Register Change Operate Instruction Class Enable i GEN General Instruction Class j XEC Execute Instruction Decode k RRRO RO RCO or ROL Instruction Group Deco...

Page 86: ... IR09 IR10 IRll IR04 IR12 IR13 IR11 IR15 GENO SRCCE CfRLE RCSE RCDE RCOE GEN XIO SKIP RBIT LDA STA JSR JMP LDBY STBY TBIT SBIT __ CMR __ IDLS Figure 6 1 I R eglster General 0 6 2 WAIT XEC 57 GENI UCE ecode ...

Page 87: ... SKN 24 SKP 2E SKM 26 REG IREG REG REG I I IREG I I Bit ID I IBit ID 1 I IBit ID I 1 0 0 1 1 0 0 0 0 0 0 IVpl i E ED SP 0 0 OVFL 0 1 LINK 0 ZERO PLUS XX XX XX XX XX XX XX XX NOTE SKIP REV XX is in 2 s complement form DISP for M 1 Base Relative EDISP for M O Program Relative M 1 Base M O Direct SKIP REV 21 XX 29 XX 2B XX 23 XX 2D XX 25 XX 2F XX 27 XX Figure 6 2 SPC 16 Instruction Summary Hexadecima...

Page 88: ...Fgister 0 l mory I II 1 REG CONTROL FUN 1 OUTPUT 1 INPUT 1 1 TEST I INTERNAL I O 1 l R 7 E 1 1 R 7 F 1 1 1 R B F 1 F F 1 3 F 1 2 3 F 1 4 3 F 1 6 3 F 1 0 1 R B E f 4 I u f 4 J 0 C U 0 Z f 4 F U F E o 1 2Rd 1 L 2Rd c Figur 6 2 continued 6 4 9 6 7 8 D 5 9 6 7 8 D 5 INTERRUPT MASK BITS ADD ADDC SUB SUBC AND ANDC XOR XORC OR ORC RTR ADDV ADDVC SUBV SUBVC ANDV ANDVC XORV XORVC ORV ORVC LDV ...

Page 89: ... 0 7 2Rd 1 DEeR 0 7 2Rd 2 ADDS 0 7 2Rd B INCR 0 7 2Rd E SHIFTS I 0 1 0 1 0 0 10 1 0 1 1 1 I 1 CNT l I I I I I 1 Rd SRLC 0 2 2Rd CNT l SRA 0 2 2Rd l CNT l SRC 0 3 2Rd CNT l SRCL 0 3 2Rd 1 CNT l CONTROL I0 I 0 I 0 0 1 0 1 1 0 0 1 SELECT I I I INE 0 4 0 3 INH 0 4 0 2 FMS 0 4 0 C BMS 0 4 0 8 LKS 0 4 3 0 LKR 0 4 2 0 PMA 0 4 4 0 SYNC 0 4 8 0 WAIT 0 0 0 X MPY 0 0 8 n DIV 0 0 A n Figure 6 2 continued 6 5 ...

Page 90: ...n the decode of bits 6 and 7 designate the I O mode which is Control Output Infut or Test type instruction M R Hemory Register select for XIO instructions The symbols and terms used in the instruction sequence charts are defined in Tables 6 1 and 6 2 respectively Symbol comma Q 2 Table 6 1 Sy bol Definition I Definition is rerl1aced by that is the term on thJ left side of the arrowhead is rep1aded...

Page 91: ...Scratch Pad Carry Out D Register Scratch Pad Data Bus Displacement Cycle Steal Request Data Transfer Into Hemory Data Transfer Into Register Data Transfer Out of Memory Data Transfer Out of Register E Register Scratch Pad Effective Address Extended Displacement End Shift Foreground Indirect Address I lput Output Bus I O Test Flip Flop L Interrupt Request Interrupt System Enable Bit L Register ...

Page 92: ...egister Scratch Pad Register and Status Counter Register and Status Counter Index Register Sequence State Shift Counter S ip on Overflow False Skip on Overflow True Shift Instruction Indicates fast overlapped ROM processing i e the sequencer goes from SS D03 to Sl D02 W Register Extended Processor Option Flip Flop Zero and Plus Indicator Zero Plus and Link Indicators Zero Plus Overflow and Link In...

Page 93: ...n see Figure 6 3 sequence state 1 Sl would be read from left to right then sequence state 3 S3 would be read and finally sequence state 5 S5 the remaining sequence states would be disregarded because they are not used by the LDA instruction The instruction sequences shown in this section may be altered in the RU mode if the dynamic SAVI switch on the rear of the console board is engaged In trouble...

Page 94: ...v this group is descr bed in detail on the following pages 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M I LI A 0 1 0 0 STA 0 1 0 1 JSR 0 1 1 0 JMP 0 1 1 1 DISP OR I EDISP 6 3 1 Load Register A LOA The contents of the locatlon as speclfled by the EA replaces the contents of the A register Refer to Figure 6 3 forl the instruction sequence chart associated with the LDA instruction The LDA instr etion is d...

Page 95: ...THERWISE NOTED OPERAND ADDRESSING J E X UJ 004 z P P l lSE W DlSP 1 IF I MSTC W L W R S3 W P EDISP DECODE I IF NOT 1 MSTC Q R Rdl IR D W L W R S5 NOT USED BY THIS INSTRUCTION W M W L W S5 NOT USED BY THIS INSTRUCTION M A _____ M L___ P S1 4 I DISP M0 9 REV 2 EDISP M0 9 WITH BIT 9 EXTEND ED INTO BITS 3 INDICATES BASE RELATIVE t 10 THRU 15 ADDRESSING EXECUTE INSTRUCTION Figure 6 3 LOA Instruct ion S...

Page 96: ...signal occurs at the en of DOC3 and places the displacement into the W register Program Relative W P EDISP If bit 11 is a zero program relative addressing is specified and the augend bus contains the contents of the P register and the addend bus contains the extended displacement Augend SLP Addend Extende Displacement f A ____ __ SMX9 SM9 SM58 SM04 A set W STW signal occurs at end 0 DOC3 and this ...

Page 97: ...ns 9 even though it is not required by LDA At DOC3 4 the contents of the destination register replace the contents the Q and R registers SSD02 A M The memory is now available and the contents of the M register data are selected onto the addend bus by SMMS6 SMS8 SM04 and loaded into the scratch pad memory by selecting register A SSD03 Nothing happens SSD04 L P The contents of the P register replace...

Page 98: ... f ro ram counter Ius hne re la the ntents _ The contents 0 the p g p p ce co of the P and r r egls ters bits 0 15 The effective address re laces the contents of the program counter and the interrupt system enable is turnedLoff inhibiting interrupt requests from being acknowledged This instruction canl ot be used in location X 7FFF Refer to Figure 6 5 The differences in this instruction with respe...

Page 99: ...P 1 ISE W DISP IF I Sl W P EDISP W L W R 3 ISE O IF NOT I Q R RdJ I R D P W L W R S1 S2 W M P W L W S1 S3 S4 I S5 I 1 DISP M0 9 2 EDISP MO 9 WITH BIT 9 EXTENDED INTO 3 INDICATES BASE RELATIVE REV BITS 10 THRU 15 ADDRESSING Figure 6 5 JSR Instruction Sequence Chart 6 15 ...

Page 100: ... except that in SlD02 the P register does not trans fer to the E register and the ISE indica or is not affected in SlD03 Refer to Figure 6 6 CIl MP I JMP is not interruptable c DOl w 002 D03 004 z W DISP if I S3 P P l ISE W L W R Sl W P EDISP Q R Rdl IR D if not I P W L W R Sl S2 S3 W M P W L W Sl S4 I S5 I 1 DISP M O 9 REV 2 EDISP MO 9 with bit 9 extended 3 INDICATES BASE RELATIVE into bits 10 th...

Page 101: ...ARS SBIT TBIT RBIT DISP I 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t REG BIT OP INDEXREG SELECT INDIRECT DIRECT OR BASE RELATIVE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M I X X 1 1 0 0 Rd Rd Rd 1 1 0 1 Rd Rd Rd 1 1 1 0 Rd Rd Rd 1 0 0 0 Rd Rd Rd 1 0 0 1 Rd Rd Rd 1 1 1 1 0 0 0 1 1 1 1 0 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 0 1 1 B I T 1 0 1 0 B I T 0 0 1 1 B I T DISP 6 17 ...

Page 102: ... D03 D04 z IF I I IF DISP 1F 2 P P 1 ISE W PISP W L P S1 IF NOT I J F I DJSP f 1F W DISP QI W L W R S3 Q R Rd IQ RJe I R D IF NOT I DISP f1F S5 W L W R IF I IF I S3 P P 1 ISE W M W L W R S2 IF NOT I IF NOT I w M QI W L W R S5 W M QI W L W S5 S3 S4 I Rd ___ M S5 L P Sl IQ R Rd 1 DISP MO 4 2 INDICATES BASE RELATIVE ADDRESSING 3 II INDICATES INDEXING Figure 6 7 _LOR Instruction Sequence Chart 18 ...

Page 103: ...irect and DISP IF W 1 W R and S3 is next If not indirect and DISP IF W 1 W R and S5 is next The base relative re gister is added to the W regis ter only if base relative addressing is specified S2D02 P P l ISE P is incremented again P l because the effective address was at the next memory location The ISE indicator is also sent through the adder and goes to the ISE flip flop S2D03 The instruction ...

Page 104: ... location specifie d by the effective address The STR instru tion is identical to the LDR instruction except that at S5D02 the contents of th R register replace the contents of the M register Refer to Figure 6 8 I en STR I I EA Rd r t r DOl D02 D03 004 z IF I IF DISP 1F S2 P P 1 ISE W DISP W L P Sl IF NOT I IFI DISP1 1F S3 W DISP Q W L W R Q R Rdl Q Rx IR D IF NOT I DISP 1 1F W L W R S5 IF I IF I ...

Page 105: ...e contents of the Q register are selected onto the augend bus and the contents of the M register are selected onto the addend bus The difference Q M is placed on the data D bus and the adder results appear in the Zero Plus Overflow and Link indicators Refer to Figure 6 9 r CMR I DB Rd EA E s E DOl 002 003 004 Z IF I IF DISP 1F p P 1 ISE W DISP W L P IF NOT I IF 1 DISP t1F Sl W DISP QI W L W R 53 Q...

Page 106: ...instructions will always reference the left half of the word bits 8 15 The right I half of the word is unchanged It is only when bits 8 9 of the byte addressing in truction are 01 10 or 11 that byte mode addressing is initiated The word addressed is then EA X 2 and right or left half depending upon X being odd or even Example A Byte addressing without ind gg__ KON EQU 5 MAY B EVEN OR ODD WORD EMOR...

Page 107: ...e is no t affected Refer to Figure 6 10 LDBY I RdO 7 EA O 7 OR 8 15 r 2 r DOl 002 D03 D04 z IF I IE DISP 1F S2 W I DISP WL P p P 1 ISE IF NOT I W DISP IF I DTSP F1F Sl S3 WL W R Q R Rd 1 Q Rx 1 R D IF NOT I DISP F1F S5 W L ____ w R IF I IF I W M W L W R S3 S2 P P 1 ISE IF NOT I IF NOT i W M t I W L W R S5 S3 W M ffl W L W S5 S4 I Rd8 15 Q8 15 IF INDEX IS EVEN S5 Rd M RdO 7 R8 15 L P Sl IF INfcEX I...

Page 108: ...e selected index register is even the right byte bits 0 7 of the selected register replace the left byt bits 8 15 of the memory location specified by the EA The instruction sequence chart associated with the STBY is shown in Figure 6 11 STBY is identical to LDBY except in S5 Only the differences are described as follows S5D02 The left or right byte is aff cted depending on whether or not the conte...

Page 109: ...SP 1 1F S5 WL W R IF I IF I W M W L W R S3 S2 P P 1 ISE IF NOT I t IF NOT I W M jl S5 W L W R S3 W M fij W L W S5 I S4 I IF INDEX IS EVEN M8 15 RO 7 S5 IF INDEX IS ODD L P Sl IQ R Rd MO 7 RO 7 1 DISP M0 4 REV 2 IF INDEXING IS NOT SELECTED 3 INDICATES BASE RELATIVE ADDRESSING THE LEFT BYTE IS THE OPERAND 4 II INDICATES INDEXING Figure 6 11 STBY Instruction Sequence Chart 6 25 ...

Page 110: ... I IF I W M W L W R S3 S2 P P 1 ISE IF NOT I jQj IF NOT I W M S5 2 W L W R S3 W M1J w t w S5 S4 I IF INDEX IS EVEN I MS OR 15 1 SS ZERO ___ MS OR 1 IF INDEX IS ODD L P Sl IQ R Rd MO OR 7 1 ZERO MO OR 7 1 DISP MO 2 IF INDEXING IS NOT SELECTED 3 INDICATES BASE RELATIVE ADDRESSING I REV THE LEFT BYTE S THE OPERAND 4 II INDICATES INDEXING FIgure 6 12 SBI T InstructlOn Sequence Chart 26 ...

Page 111: ... in the specified bit position 0 7 in the right byte of the memory location as specified by the effective address If the index is even place a zero in the specified bit 8 15 in the left byte of the memory location as specified by the effective address Refer to Figure 6 13 en RBIT I EA 0 OR 15 E 2 E 001 D02 003 004 z IF I W DISP IF DISP 1F S2 P P 1 ISE IF NOT I fiJ W L P Sl W DISP 2 IF 1 DISP F1F S...

Page 112: ...e Zero indicator accordingly If the inde is even test the specified bit 8 lS of the left byte of the location as specified by the effective address Set t e Zero indicator accordingly Refer to Figure 6 14 This instruction is identical to the SBIT instruction except that no bits are affec ted in the specified memory location 6 4 10 Increment Memory INCM The contents of the memory location as s ecifi...

Page 113: ...S5 WL W R IF I IF I 52 P P l ISE W M W L W R S3 IF NOT I fz IF NOT I W M W L W R S5 S3 W Mfi W L W S5 S4 I IF INDEX IS EVEN S5 ZERO ___ M8 OR 15 L P Sl IF INDEX IS ODD IQ R ___ Rd ZERO MO OR 7 1 DISP MO 4 2 IF INDEXING IS NOT SELECTED 3 INDICATES BASE RELATIVE ADDRESSING REV THE LEFT BYTE IS THE OPERAND 4 II INDICATES INDEXING Figure 6 14 TBIT Instruction Sequence Chart 6 29 ...

Page 114: ... W L W R S3 Q R Rd 1Q Rx I I R D IF NOT I DISP f 1F S5 WL W R IF I IF I P P 1 ISE W M W L W R S3 2 IF NOT I IF NOT I W M Q W L W R S5 II W M Q W L W II 3 S5 I M M l L P Sl 5 ZPL ADDER IQ R Rd RESULTS l DISP MO 4 REV 2 INDICATES BASE RELATIVE ADDRESSING 3 II INDICATES INDEXING F guce 6 15 NCM J uct on Sequence Chact 30 ...

Page 115: ... 153 Q R Rd I Q Rx 1 R D IF NOT I DISP FiF S5 WL W R IF I IF I P P 1 ISE W M W L W R S3 S2 IF NOT I IF NOT I W M Q W L W R S W M Q W L W S5 S3 S4 I M M l L P S5 Sl ZPL ADDER IQ R Rd RESULTS 1 DISP MO 4 SHT NXT REV 2 INDICATES BASE RELATIVE ADDRESSING 3 II INDICATES INDEXING Figure 6 16 DECM Instruction Sequence Chart 6 31 ...

Page 116: ...LO EA 8 5 PLUS EA 8 6 ZERO EA 8 7 FOREGROUND EA 8 8 The LARS instruc t ion is identical to the LDR in sequence states Sl S2 and S3 Sequence states S4 and S5 are described r n the following paragraphs Refer to Figure 6 17 S4D02 R M When S4D02 is first ntered the number in the regi ster status counter tft C is zero being cleared luring Sl The contents of the M register replace the contents of the re...

Page 117: ...F S4 W L W R IF I IF I P P 1 ISE W M W L W R S3 S2 IF NOT I IF NOT I W M Q W L W R S4 W M Q W L W S4 S3 R M W W l IF RSC 1 8 4 rsc W L W S4 RSC RSC l IF RSC 8 I W L W S5 FRGND SS ZPOL SC M L P Sl IQ R Rd 1 DISP MO 4 3 0 INDICATES BASE RELATIVE ADDRESSING REV I 2 RSC IS CLEARED DURING S1 4 II INDICATES INDEXING Figure 6 17 LARS Instruction Sequence Chart 6 33 ...

Page 118: ...he ne t memory location In D04 the test RSC 8 is made and t is equal to 8 The next memory location transfers to the Wand the L register and the sequencer goes to SsDOl SsD02 FRGND ZPOL and SC M The co tents of the M register transfers through the adder and onto the data bus and t e following bits go into the FRGND ZPOL indicators and the shift counter Data Bus Bit Indicator or Shift Counter DBOO 0...

Page 119: ... 1 IF I DISP FIF W DISP Q W L W R Q R Rd I Q Rx I R D IF NOT I DISP t iF W L W R IF I IF I P P 1 ISE W M W L W R S2 IF NOT I IF NOT 1 W M Q W L W R W M Q W L W S3 M R W W l IF RSC F8 S4 W L W RSC RSC l IF RSC 8 IQ R Rrsc W L W M FRGND L P SS ZPOL SC IQ R Rd 1 DISP MO 4 t z S2 S3 S4 S3 S4 S4 S4 SS Sl REV 3 INDICATES BASE RELATIVE ADDRESSING 2 RSC IS CLEARED DURING S1 4 II INDICATES INDEXING Figure ...

Page 120: ...ives oUf next memory location and the sequencer goes back to S4DOI The first time thr ugh the 100P RSC O At the end of D00 memory start clock is issued The next time through the loop RSC 1 and the contents of the X register replace the contents of the M register This loop continues until RSC 7 and the E regist r is l aded into M At D03 the RSC is incremented and it now contains the nu ber 8 The W ...

Page 121: ...not met the next instruction in sequence is executed Refer to Figure 6 19 CI SKIP I 001 D02 Z P P 1 ISE Sl S5 f Q R Rdl z 003 004 CONDITION MET P P EDISP L P Sl SKOT OR SKOF OFLO O S5 1 EDISP M0 8 WITH BIT 8 EXTENDED INTO REV BITS 9 thru 15 Figure 6 19 SKIP Instruction Sequence Chart 6 37 ...

Page 122: ...L P OFLO 0 SKOF or SKOT If the instruction is a SKOF or SKOT the OFLO indicator will be reset after the condition is tested The contents of the P regis ter replace the contents of the L register and the sequencer goes back to Sl 6 6 INPUT OUTPUT INSTRUCTIONS XIO 6 6 1 XIO Control and Test Instructions CTRL TEST I0 I 0 I 0 I 1 I I I I I I I1 0tDID E S 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I O MODE ...

Page 123: ... the processor and I O devices Refer to Figure 6 20 tI XIO I CfRL TEST Ri 001 002 003 004 z p P 1 ISE Sl S5 Q R Rd I R Rs I W L w S2 S3 S4 I IF TEST lOT I O CABLE TEST LINE L P S5 IF TEST lOT Sl P P l ISE IQ R Rd IF TEST NOT lOT P P REV Figure 6 20 XIO Control and Test Sequence Chart 6 39 ...

Page 124: ...t is the contents of P replace the contents of P The next instruction in sequence P l is executed SSD04 L P The contents of P replac the contents of the L register and the sequencer goes to Sl 6 6 2 XIO Data Transfers The XIO data transfer instruction is iden ical to the XIO Test and Control in SlD02 The difference thereafter are described ih the following paragraphs Refer to Figure 6 21 I SlD03 W...

Page 125: ...TTR DTOR OR RSCR S5 W L Q R Rdl I NO MEMORY START R Rs CLOCK NO CLEAR M S2 S3 S4 I DTOR I O M DTIR Rs 1 0 RCSR Rs I O tt L P Sl S5 DTOM I O M IQ R Rd DTIM M I O RCSM M I O tt SHT NXT REV t t Source data for RCSR RCSM is from console switches Figure 6 21 XIO Data Transfer Sequence Chart 6 41 ...

Page 126: ...es the contents of the M regis ter I SSDo4 L P The updated p reeistel replaces the contents of the L register and the sequencer goes to Sl r 6 7 REGISTER OPERATE AND REGISTER OPERA E COMPARE INSTRUCTIONS The instructions in this group are of thd format shown below The decod es of the instruction ar so s wn I lo o o o l l I R I R I I t I 15 14 13 32 i1 0 0 0 0 1 I 15 14 13 12 t10 9 8 I 6 5 4 OPCODE...

Page 127: ...Results I REV Figure 6 22 Register Operate Instruction S equence Chart p __ ______ A ______________ r o o o o I O IO I O I l I E G I I I I r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OptODE J t EXTENSION LOV 0101 LOAD COMPARE ADD 1001 0 COMPARE 1 LOAD SUB 0110 OR 1101 XOR 1000 ANn 0111 6 43 p 1 r LITERAL VALUE I I I I I I I I I I 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

Page 128: ...gisters The P counter is incremented and placed back into p 1The source register decoded by bits 8 9 and 10 replace the contents of the Rr register The sequencer then goes to S5D03 S5D03 Different events occur dependinl g on the state of bit 4 Assume Bit 4 is off therefore a compare is specified The Q register contains the destination register and the R register contains the source register The AL...

Page 129: ...Overflow Link I f COMPARE is specified the operation requested is performed and the conditions of the results are placed into the indicators The destination register Rq remains unchanged Refer to Figure 6 23 SlD02 Q R Rd P P l ISE The destination register decoded by bits 5 6 and 7 of the instruction replace the contents of the Q and the R registers Then the P counter is incremented and is placed b...

Page 130: ...SE L P S1 S5 Q R Rd I I R D P P 1 ISE DB Q Operate M L P J IF LOAD J Rd DB S5 IF ADD OR SUB S1 ZPOL ADDER RESULTS IF NOT ADD OR NOT SUB ZP ADDER RESULTS IQ R Rd I REV r Figure 6 23 Register Operate Literal Instructlon Sequence Chart 6 46 ...

Page 131: ...he P counter has been incremented twice once in SlD02 and the second time in SSD02 The contents of the P counter replace the contents of the L counter and the sequencer goes to Sl 6 9 REGISTER CHANGE INSTRUCTIONS There are 16 instructions in the Register Change group and each of these instructions is of the following format o I I I I I I 15 14 13 12 11 10 Y 7 6 5 I BITS INSTRUCTION BITS 9 8 43210 ...

Page 132: ...e sequencer then goes to S5 S5D03 Various operations occur depend ng on the bit configuration of bits 0 4 The operations are described as followk Register Add Link Rd Q Link The Q l egister now contains the destination regis ter The contents of the Link indicator are added to the Q and the sum replaces the destination register decoded by bir S 5 6 and 7 The ALU results affect the Z p and L indicat...

Page 133: ...S5 r S1 r X Q R Rd I R Rs Z 003 D04 Rd Q LINK RLK Rd Q S ADDS L P S1 Rd Q 1 INCR Rd Q 1 DECR Rd NOTQ CMPL IF RLK S5 ZPOL ADDER RESULTS IF NOT RLK ZPL ADDER RESULTS REV Figure 6 24 RLK ADDS INCR DECR CMPL Instruction Sequence Chart 6 49 ...

Page 134: ...nstruction sequence chart in Figure 6 25 is associated with the following register change instructions Zero Right Byte ZRBY Zero Left Byte ZLBY Read Console Switches RCSW Zero Register ZERO RCD J I DOl D02 P P 1 ISE Sl Q R Rd I I S5 1 RdL Rd 8 15 2 RdR Rd 0 7 _ f 4 Z S5 D03 RdL RL RdL RR RdL CSWL RdL FRGND RdR R RdR RL RdR CSWR Exchange Byte EXBY Transfer Status to Register TSR D04 ZRBY EXBY L P S...

Page 135: ...en into the destination register No select into the ALU for the left byte yields zeroes in bits 8 15 of the destination register Exchange Bytes RdL RR RdR RL A select R register right to left SRRL causes bits 0 7 of the R register to be transferred to bits 8 15 of the destination register A SRLR causes bits 8 15 to be transferred to bits 0 7 of the destination register Read Console Switches Rd L C...

Page 136: ...s associated with the following register change instructions en s E Sl S5 Display Register DSPL Transfer Register to Status TRS Restore Interrupt System Enable I ISE Subroutine Return RTRN Execute Register Contents XEC RCS I E DOl D02 I Z IF NOT XEC IF NOT XEC I NO ACTION P P l ISE S5 IF XEC IF XEC P P ISE M Q Q R Rd I R IRs K Q D03 F GND ZPOL S 1 FOR FAST OVERLAPPED ROM PROCESSING ONLY ISE ____ Q...

Page 137: ...ansfer Register to Status FRGND ZPOL and S Q The contents of the Q register are transferred to FRGND Z P 0 and L and the shift counter Restore ISE ISE Q15 Bit 15 of the destination register which is in Q is transferred to the ISE indicator Transfer Register to P P Q The contents of the destination register Q replace the P counter This is the subroutine return instruction Execute M Q This only happ...

Page 138: ...NT X O 08 1 SHIFT The number of shif ts specified is bits 5 6 and 7 as follows r F 178 16 SHIFTS performed The destination register is specified by Bit Code 765 000 o 0 1 o 1 0 o 1 1 1 0 0 1 0 1 1 1 0 Register A X Y Z B C D Refer to Figure 6 27 for a Sh f nstructl on flowc art and to Figure 6 28 for the instruction sequence chart for the shift instructions 6 54 ...

Page 139: ...27 Shift Instruction Flowc art C SHIFT 1 s E DOl D02 Z P P 1 ISE S5 Sl SC O r X Q R Rd I R Rs Z D03 D04 Rd 14 0 Q15 1 SC SC l L P Sl LINK QO SRA Rd15 Q15 SRC Rd15 QO SRLC Rd15 0 S5 SRCL Rd15 LINK ZPL ADDER RESULTS IF ENDSR r I Q Rd 1 IF NOT ENDSR REV Figure 6 28 Shift Instruction Sequence Chart 6 55 ...

Page 140: ...nd the shift counter is incremented This continues until the ENDSR signal occurs One shift is accomplished for each pass through S5D03 Shift Right Circular SRC Rd15 oo f The destination register Q is shifted right the number of positions sp ecifie by the shift count Bit 0 of the Q register is shifted into bit 15 of the destination register Bits are shifted out of bit 0 into LINK Bits shifted out o...

Page 141: ...to S5D04 where it terminates One shift is accomplished for each pass through S5D03 S5D04 L P The contents of the P counter replace the contents of the L register and the sequencer goes back to Sl 6 11 CONTROL INSTRUCTIONS The eight instructions in the control grou are of the following format The instruc tion sequence chart associated with the Control instructions is shown in Figure 6 29 10 0 0 010...

Page 142: ... Z P P 1 ISE S5 Sl Q R Rd I UJ z 003 D04 SYNC I l SYNC OMA INIT PMA L P Sl LINK O LKR LINK l LKS FRGN O BMS FRGND l FMS ISE O INH S5 ISE l INE REV Figure 6 29 SYNC PMA LKR LKS BMS FMS INH INE Instruction Sequence Chart 6 58 ...

Page 143: ...INK O This instruction places a 0 into the LINK indicator Link Set LKS LINK 1 This instruction places a 1 into the LINK indicator Background Mode Set BMS FRGND O This resets the foreground flip flop and sets the processor into the background mode Following the execution of this instruction the eight background registers A X Y Z B C D and E are used by all instructions that specify registers The fo...

Page 144: ...utine S5D04 L P The S5D04 state is conuno1 to all instructions in this group The contents of incremented in Sl P counter replaces the contents of the L register 6 12 WAIT INSTRUCTION The WAIT instructi on is of the following format Refer to Figure 6 30 for the se quence chart associated with the wait instruction 1 0 0 0 0 1 0 0 0 1 0 1 OPTIONAL I _ I I I _ I I 11 _ c I I I I I 15 14 13 12 11 10 9 ...

Page 145: ...same memory location is accessed S5D04 L P The contents of the P counter replace the contents of the L register and the sequencer goes to Sl 6 13 MULTIPLY MPY OPTION The optional thardware multiply has the following characteristics a Fixed point b Positive numbers only c Variable length The registers involved in the multiply instruction are shown below The op code hex is 15 Register o A C B C 12 8...

Page 146: ...IF LINK 0 l I Q I W B W 2 IF LINK 1 C Q W B W R 2 T C1S LINK LINK WO LINK DBOO XPOF O SC SC l S9 S9 IF END SHIFT IF LINK 0 W B Yi SS 2 IF LINK 1 I W B W R D04 2 C1S LINK LINK DBOO Q LINK WO SS C 2 L P Sl C I A MULTIPLCAND REV C MULTIPLIER i B C PRODUCT A x C Figure 6 31 MPY Irstruction Sequence Chart 6 62 ...

Page 147: ...ertain events described later occur in D03 then the sequencer goes back to S9D02 This loop continues until the end shift signal occurs and the sequencer goes to SSD03 If LINK contains a zero the W register is shifted right one place and placed back into Wand the B register In the sequence chart W 2 indicates a right shift If LINK contains a one the W register is shifted right one place and added t...

Page 148: ...r contains F 15 Again assume the multiply op code is _8F out this time the C register contains the following 15 14 13 12 11 10 7 6 543 2 1 0 C REGISTER I0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 I I I I I I I I I I I I I I I I I b t The C register contains FO 15 Assume the multiply op code is 84 and the C register contains the following 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 C REGISTER I 0 0 0 0 0 0 o 0 0 0 0 1 ...

Page 149: ...A register OOOF The sum of this addit on is placed in B The B register could contain anything the first time through L2 means the value of link after D02 W register bit 0 which is a 0 is placed into LINK and the XPOF flip flop is reset The sequencer then goes to S9D03 In S9D03 the contents of C replace the contents of Q The value of the shift counter is 0 at the time The Q C register is shifted ri...

Page 150: ...0 ENTER Ss D03 XPOR I C REG INQ A ter 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P 02 I I I I R 0000000000001111 o 0 0 0 0 0 0 0 0 0 0 0 6 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 o 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 000 0 0 0 0 o 1 1 1 o o o o o o o 000 1 0 0 0 0 0 0 0 0 0 0 0 0 o 0 0010 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 O 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0...

Page 151: ...tions In a divide instruction n must be large enough to ensure that alII bits in C prior to division will be shifted left out after n shifts The registers used in a divide instruction are as follows Register A B C B C NOTE Function Divisor Dividend most significant Dividend least significant Remainder after division Quotient B C A The number in B before division must be less than the number in A T...

Page 152: ...wn in Figure 6 33 I I I en DIV I I I t f I 001 002 Z P P 1 ISE SC O Sl XPOF 1 S5 Q R C I R A D03 I 5 W Q S9 LINK O I I 004 If not END SHIFf I DB Q R C W W W LINK B Q Q LINK LINK COur LINK cour I LINK CCOur XPOF O SC SC l S9 Q B I I IfDB15 0 I S9 If END SHIFf k B DB c W W W LIN LINK COUT I S5 Q B I Q B I I 55 L P Sl 1 I REV r I F gure 6 33 DIV 11 uc on Sequence Cha 6 68 ...

Page 153: ...ns to cause the augend to add to itself LINK is added to it and Q is then placed into B The carry out is placed into LINK The shift counter is incremen ted compared to the number in I and placed back into the shift counter The sequencer then goes to S9D04 S9D04 Q B The contents of B replace the contents of the Q register The sequencer then goes back to S9D01 S9D01 DB Q R LINK COUT If DB15 0 B DB Q...

Page 154: ... S8 D04 through S8 D03 at which time the previously active sequence jstate D04 is continued Turn indicates that fast overlapped Pljocessing is taking place The conditions for turning are ROM and non memory referencing INTERRUPT AND CYCLEJ STEAL SEQUENCING I I THIS NEXT NEXT 001 002 I I 003 004 ANY NORMAL I NORMAL S ACTIVITY O CR ACTIVITY SS 004 I TURN XPOF S5 004 SRI ENOSR i REO S1 001 L P TURN S1...

Page 155: ... of a typical mag netic core is shown in Figure 7 2 With the core unmagnetized an increasing magnetizing force H increases flux density B on an S shaped curve As the core nears saturation an increase in H causes little change in B because the core cannot support a greater flux When the magnetizing force returns to zero the flux in the core remains nearly the same the core has remembered the magnet...

Page 156: ...R02 LR01 LROO Y CURRENT 2 WRSE RDSE X CURRENT 2 LR06 LR07 LR08 LR09 LR10 LR11 x DECODER AND DRIVE SWITCHES TEMPERATURE COMPENSATION REGULATOR CURRENT ADJ 8 SOURCE LINES 8 SINK LINES SENSE AMPLIFIER SA 18 TO M REG ONLY 16 BITS ARE USED 4K 16 BIT MODULE WITH DIODE DECODE MATRIX STRB 1 S SOURCE LINES 8 SINK LINES THERMISTOR 1 INHB 1 MDXX S X S X 6XS v r 4096 LOCATIONS 16 PAIR INHIBIT CURRENT INHIBIT ...

Page 157: ...mains When negative full select magnetizing current reaches coercive strength the core is switched to negative saturation When current is reduced to zero most of the flux remains When positive full select magnetizing current reaches coercive strength the core is switched back to positive saturation In memory operation the core never returns to zero flux Figure 7 2 Ferrite Core Hysteresis Loop 7 3 ...

Page 158: ...pposite direction of the X and Y drive cur rent The inhibit drivet produces full select current which is equally divided i n the two sections of the sense inhibit line transformer When a bit is inhibited the net curren throbgh the core is 1 2 select which is inadequate to switch the core to the 0 state When a bit is read a voltage is induced in the sense inhibit line if t he core switches from the...

Page 159: ...en w Z w a c X o I I I I 30 31 32 33 I I I I 62 63 o INHIBIT DRIVER TO n 1 BIT MATS 1 30 31 32 33 62 63 TO n 1 BIT MATS Y DRIVE LINES Figure 7 3 Memory Core Mat 7 5 ...

Page 160: ... octal decoder is grounded which is dependent u on the binary representation of the address bus input If a read cycle is to lbe performed RDSE goes positive forcing current through Rl the primary of Tl and into the decoder sink The current in the primary of Tl is coupled to the secot dary and turns on Ql allowing current from the current source to flow into the diode decode matrix and module Con v...

Page 161: ...i I e J x S CD c CD CURRENT SOURCE Rl AD SOURCE SWITCH WRITE SOURCE SWITCH READ SINK SWITCH WRITE SINK SWITCH I MORY I I I I 15V I I TO 7 OTHER t SOURCES 7 OTHER I SINKS I I I I 64 x 16 CORES I I I 1 2 SELECT READ I I 1 2 SELECT WRITE I 15V L J 15V 15V ...

Page 162: ... en ii n T en n T CD 3 c LRXX LRXX LRXX ABEN BINARY TO OCATAL DECODER 5V CR3 CR1 o TO 7 OTHER SWITCH ES RDSE TO 7 OTHER SWITCHES R1 CR4 T2 CR5 R2 WRSE CR2 o TO 7 OTHER SWITCHES CR6 5V X1 OR Y1 TO DECaDE MATRIX AND MODULE xf OR Y ...

Page 163: ... 15V __ __ e e_ R4 C1 CRI R5 Q1 CW R9 A XRV J N YRV R7 Rl0 THERMISTOR THERMISTOR R2 XYDR R3 Figure 7 6 Regulator Schematic 7 9 ...

Page 164: ...4 Current Turn On The MGRD is still at 15V When IEN g es high Q goes off Q goes off Q 2 goes on and the current Q charges C 2 in a inear posi ive ramp wit6 respect to 15V The current through 8 R Qg Ql0 and Ql 1 also increase in a linear ramp When the voltage across C 2 witfi respect tm 15V lS at final value the current from Q 4 is clamped through Rg CR 1 and Q 3 and the current through Q Qg QI0 an...

Page 165: ...CR5 15V 14 R4 Rl0 R21 XI XRV Rl 5V R15 lUI 5V L7 1 c c R22 CR6 R12 c Ci EN R8 J X IEN XI J I I R13 I en 0 C en C 11 15V CR2 T 3 i R3 R20 I 15V C MGRD R2 C3 AI 15V ...

Page 166: ... cycle Q2 and Q are off If a core switches in the 4096 core mat when the X and Y drive curren s are applied the core output is applied to the sense amplifier The core output is ampl lfied threshold detec ted by the adj us table threshold voltage THRV and ANDed with he strobe STRB in the sense amplifier 23 inverts the sense amplifier output an applies it to a flip flop of the memory data register R...

Page 167: ... G co I I I I I I I L ct ct c I OJ ct I w en I ct w 0 ct I u 0 u u 0 OJ I l e 0 N I a I L ____ l I I I I I I _ ___ 1 LO co ct ct Figure 7 8 Sense Amplifier and Inhibit Driver Schematic 7 13 e ct N ct u ct u x x Cl en co c z II M N N iI Z II ...

Page 168: ... I 90 60 50 STl OR MSTC1 K INVALID X V SWITCH INHT DOC12 IEN YI 135 NS I D01 180 120 100 270 180 150 360 240 200 90 60 50 DOC1 D02 180 120 100 270 180 150 720 480 40 D03 EJ DOC2 12 Ld DOC2 IJ DOC4 121 READ WRIT 235 NS CURRENT ENABLE 1 I SA 1J DOC3 t 2l MSTC2 _ tl MTIM FOR INHT zI SETM f A I OOD VA VJ ClM I ...

Page 169: ...l A Inhibit time control B 20V inhibit driver voltage Inhibit time Location register bits Memory cycle Memory register bits Memory guard relay The presence of this signal on the memory boards inhibits X and Y drive current to the memory module s Memory stack select Memory start clock Current source enable Read witch enable Read out of memory Sense amp bits Strobe sense amps Threshold voltage Write...

Page 170: ...to module X drive current XYDR XY15 X Y drivJ l5V to X l nd Y lines XYRV X Y temperature compensated regulator voltage YOA through Y7A YOC through Y7C Y drive anode output to module Y drive cl thode output to module I YI y drive current Y50 through Y57 Y drive sink output to module I 7 16 ...

Page 171: ...th PFD and RS are at ground Figure 8 1 is a timing diagram illustrating the manner in which a power failure sequence is initiated if an interruption of the AC line voltage causes DC voltage in the computer to fall below prescribed operating levels The power failure detection circuit monitors the unregulated DC voltage to detect the improper power condition If the AC input voltage drops below 105 v...

Page 172: ...low 10j vac 200 vac European for longer than 1 millisecond t he power failure detection circuit requests an interrupt and triggers the power shutdown sequence At Ithe time the interrupt is requested the OHA timer is init ialized to time out in 00 R H memory cycles and any f urther PHA instructions or DMA requests are ignored 1 Therefore after the power fail inter rupt request the program has 100 R...

Page 173: ... of dust and dirt probably indicate malfunctioning of the fans Such accumulations in electronic circuits act as an insulating blanket by preventing efficient heat dissipation and trap moisture The former condition causes over heating and subsequent component breakdown the latter condition allows signal crosstalk If a fan becomes inoperative it should be replaced immediately 9 1 1 Fan Removal and R...

Page 174: ...AC LlNE CORD GROMMET SLOT o FAN ASSEMBLY SIDE PANEL GROMMET FRONT CONSOLE SIDE PANEL RETAINING SCREWS 6 SCREWS 4 I FAN FAN CONNECTOR PINS Figure 9 1 Removing Fans All Models 9 2 ...

Page 175: ...ied in the course of routine or preventive maintenance as well as during troubleshooting The 5V 15V and 15V levels may be checked by measuring certain external pin locations on the Master Interconnect Board Each voltage level should be within 2 of the specified value If a voltage is found to lie beyond these tolerances an internal power supply adjustment is required PROCESSOR POWER SUPPLY VERIFICA...

Page 176: ...ers a pzy to both the SPC 16 40 60 80 andl 45 65 85 series If the above AC ripple limits are exceeded the power supply should be replaced If an output level adjustment is reqUire a separate voltage adjustment potentiometer is provided in the power s pply for each output SV lSV lSV and 20V To gain access to the potentiometers 1 Remove the power supply assembl from the rack or cabinet in which it is...

Page 177: ... o o o o POWER SUPPLY BOTTOM VI EW COVER REMOVED 15V VOLTAGE ADJUST 7 15V VOLTAGE ADJUST 7 I f 5V VOLTAGE ADJUST 20V VOLTAGE ADJUST Figure 9 3 Power Supply Adjustment Potentiometers 9 5 o o o ...

Page 178: ......

Page 179: ...lay Console Section 10 3 o Check power supply Section 9 2 o Replace processor boards with available spares Section 10 5 The above are arranged in decreasing priority That is since the test programs often serve to pinpoint a malfunction with minimum troubleshooting time invested they are the logical first step in many maintenance procedures If the test programs load and execute properly they can in...

Page 180: ...1 Timing 31D01811A Macro 31D013311 Arithmetic 31D01333A MIO 31D01628A MIB SPC 16 31D01640 t 40 60 80 MIB SPC 16 31D 1 01648 45 65 85 Mem Expansion MIB SPC 16 45 65 85 4K Memory 8K Memory 16K Memory Logic Drawing Number 90C01446A 90C01811A 90C01331A 90C01333A 90D01628A 90D01640A 90D01648A 90D01650A 90D01635A 90D01594A 90D01783A The following tools are ing subassemblies 31D01650A 3lD0163S4 31D015941...

Page 181: ... 5 0101 5 13 1101 D 6 0110 6 14 1110 E 7 0111 7 15 1111 F Numbers having a base of 16 i e hexadecimal numbers are formally represented with a subscript 16 just as the standard numbers base 10 decimal are repre sented with a subscript of 10 and binary numbers are given a 2 subscript So it can be written that In this section an X and lower case quotation marks are used in place of sub scripts to den...

Page 182: ...d another program automatically Two data formats are used for pJ ograms bootstrap binary and PGS binary Most system software as well as the object tapes of user programs that have been assembled or compiled are in PGS for at The Teletype Test and Verify Program is in PGS format The smallest loadin program that will accept programs in PGS format is the PGS Loader it consists of more than 250 instru...

Page 183: ...ied with a High Speed Paper Tape ROM will load binary tapes LOADING THE TELETYPE BOOTSTRAP The Teletype Bootstrap will be loaded into the eight memory locations X 005l through X 0058 Hexadecimal 0620 0524 10FF 73FE l8BF 9900 072E 73F9 Instruction ZERO LOOP DSPL TEST JMP DTIR STBY INCR JMP Operand X X RDY TY 1 A TY A O X l X LOOP In the discussion which follows the circled numbers refer to switches...

Page 184: ...oader instr uc tions Disengage SAVE I switch Depres s SYSTEMS RESET Verify that the bootstrap was keyed in c9rrectly by displaying the eight memory loca tions as follows I r Repeat steps b rough j WiJh the exception that in step h the Data Entry switches 2 should be Jet to hexadecimal code X 4000 which loads the A register with the contej ts of memory as specified by t he P register s Press STEP T...

Page 185: ...MS RESET 5 Set the RUN IDLE switch to RUN 6 Press STEP switch 7 Turn the reader on 8 When the program has been loaded turn the reader off The loading process doesn t stop after the last data byte has been read but continues until the physical end of the tape is reached or until the reader is turned off 9 Set the RUN IDLE switch to IDLE 10 Depress SYSTEMS RESET The above procedure will be used to l...

Page 186: ...ap may be keyed in by hand The loading procedure is given in steps Ja through u of the paragraph titled Loading the Teletype Bootstrap however the HSPTR Bootstrap s address minus one in step d is X 0058 I EXECUTING THE HSPTR BOOTSTRAP With the High Speed Paper Tape Reader B90tstrap in me ory programs supplied on binary formatted paper tape may be loaded as follows 1 Set the D register to the start...

Page 187: ...nuals give all the necessary information needed to load and exe cute these programs They also supply an error directory that can be used to isolate the malfunctioning component VERIFICATION OF TIMING BOARD OPERATION Upon encountering an error the Processor Test Verify Program puts the processor in a WAIT state Since the processor remains in this state until the STEP switch is pressed the technicia...

Page 188: ...s may be scoped are given in Table 10 1 A or _ suffix on a signal mnemon c indicates true or complemented signal respectively 1 1 R W MEMORY CYCLE 800 960 or 1440 nsec Q MC MC DOC1 ________ _r__l __ r l r l r DOC2 DOC3 DOC4 r__l r r__l r L 0 001 J L 200 240 380 002 1 L 400 480 760 003 I 600 720 1140 004 L 51 J L 55 J L Figure 10 1 Timing Diagram WAIT 10 10 ...

Page 189: ... I O bus for DMA operations but this section is written based on a General Automation module A single Data Channel Module provides eight high speed channels and will service up to eight peripheral controllers It maintains a block count register SCR and an address register CAR for each active d ta channel The block count re gister specifies the number of data items to be transferred it is decrement...

Page 190: ...programl initiated DMA operation using the chaining mode The operations performed in this mode are similar to the operations per formed in the initiate mode However lit retrieves each new CAR from the locations specified by the current CAR and the n1 ew SCR from the location specified by the new CAR A complete description of the MHSDC 8 l together with test procedures is given in GA s Multi High S...

Page 191: ...und mode registers with data from the console and then displays it on the Register Display indicators to visually check the validity of the round trip display to register and back transmission Data transmitted tq each register varies from data to the previous register so that the Register Select hardware may be checked at the same time The register loading sequence is a Disengage Register Select s...

Page 192: ...EO FFCO FF80 FFOO FEOO FCOO Disregard value of bit 15 for P register 1 Visually check whether all rl egisters above do indeed contain the values listed by sequentially disp ayi the contents of each using the approp riate Register Select switcHes through If a discrepancy occurs betwJen the expected contents and the indicated as displayed contents of a register he desired data should be re keyed ont...

Page 193: ...es have been loaded into the At register g Load the rema n ng Gener l Purpose registers foreground mode by the following sequence Set Data set Gen Pur press Entry switch __ t_h_en __ Select switches __ th_e_n __ I ENTER CD to 7 001 6 010 5 011 4 100 3 101 2 110 1 111 At this point the General Purpose registers in the foreground mode should be loaded with values differing by one Register Display In...

Page 194: ...ll appear unlit for all registers where tiey should appear lit 2 Augend Addend Data Bus 0 1Arithmetic Logic Unit malfunctioning Data transmission error iIljvolving several registers is probably due to malfunctioning of ne of these elements Since they are all located on the Arithmetic Board the Arithmetic Board is probably the best board tol replace in a multi error situation If only the General Pu...

Page 195: ...ng buses or ALU The Arithmetic Board should be re placed P or W registers appear erroneous Bus or register malfunctions related to these registers signal replacement of Arithmetic Board Status register appears erroneous Buses related to the Status register are located on the Arithmetic Board the Status register itself is lo cated on the Macro Control Board However if the Status register is the onl...

Page 196: ...uction memory location X OEFF mhst be loaded with a value of OOFO In performing this task the integrity of l the direct addressing mode is tested Load location X OEFF as follows a Select P register switch 1 b Set Data Entry switches 2 to X OEFE Since the P register will be incremented before the data is loaded into memory this step indicates that the memory location selected is X OEFF c Press ENTE...

Page 197: ...ssion has occurred between the registers and memory the Register Display Indicators will display X OOFO MEMORY TRANSMISSION ERRORS DIRECT ADDRESSING If the Register Display Indicators do not display X OOFO however erroneous console communication with memory is indicated Therefore malfunction exists in either the Memory and Input Output MIa Arithmetic or Timing Board Perhaps the easiest first check...

Page 198: ... is easily accomplished by re doing steps a through m above bJ t using X OIOO and X AAAA as the Data Entry Switch values in steps b and j respectively LOADING TEST INSTRUCTION INTO MEMORY 1ROM CONSOLE There are two ways to execute the tes instruction Certainly the simplest way is to load the instruction into the I l register and execute However since the purpose of thi s manual is to troublesHoot ...

Page 199: ...10 2 TOP i 1 D Disp OEFF 1_ 1 OOFO r EA 0101 AAAA 0021 I CD02 0000 __ LOCATION CONTAI N ING BASE RELATIVE ADDRESS TO WHICH INDE IS ADD ED LOCATI ON OF OPERAND LOCA T ION OF LD R INST RUCTI ON Figure 10 2 Memory Allocation for Base Relative Indirect LOR Instruction With Inde ing 10 21 ...

Page 200: ...ral Purpose Register Select switches to 110 Press ENTER D register is loaded Disengage General Purpose Regl ster Select switches FETCH AND EXECUTE INSTRUCTION Now that the memory an the appropriate l egisters have been loaded all that remai ns is to address the memory location containing the test instruction 002l and execute The sequence is as follows a Select P register switch b Set Data Entry sw...

Page 201: ...ry switches 2 to X 0020 c Press ENTER C d Disengage P switch e Select I register switch f Set Data Entry switches j to x 4000 which is the pattern for LDA 0 0 g Press ENTER C h Select SAVE I switch 2 i Disengage I register switch j Press STEP switch At this point if the Register Display Indicators display X CD02 continue to step k If not the LDR instruction was not properly loaded into memory and ...

Page 202: ...r Dir ee t Addr essing Verification of the contents of the preceding memory locations eliminate the Memory and Input Output Board as the source of error The Arithmetic Board has been ex cluded as a source of error by previous tests in this section Further the previously executed JlLDA and IlSTA instructio s juS tify exclusion of the Timing Board as the faulty element The conclusion one must reach ...

Page 203: ...tion is as follows 1 Remove power from the computer 2 Exchange CPU boards with available spare boards 3 Re apply power and check to see whether malfunction is still present If mal function remains go to Section 10 3 if not continue 4 If the replacement of several spare boards has eliminated the malfunction exchange the spares now in the console with their original board counter parts one by one ve...

Page 204: ...or the subassemblies 10 6 1 CPU t1emory and Contro11 er Boar All printed circuit boards mounted in a card rack CPU memory and peripheral controller boards are removed and installed through the front of the cabinet To do this first open the console panei 90 0 Do not strain the two ribbon cables connected to the console board lhen remove the desired board by pulling on both e tractor tabs J CA ITION...

Page 205: ...ler boards on one side of the board and connectors for outside cabling on its reverse side The 40 60 80 models have one MIB 45 65 85 models have two SPC 16 40 60 80 SERIES MIB Removal of the MIB may be required to check the condition of the board or connectors on the poard The procedure for removal and replacement of the MIB is provided be low Figure 10 4 illustrates this procedure 1 Disconnect th...

Page 206: ...CREW I O CONNECTOR GUIDE ENCLOSURE DISCONNECT BOTH CABLES INSIDE OF MIB INSULATOR RETAINING SCREWS AC LINE CORD RUBBER GROMMET PROTECTIVE MATERIAL f MIB EXPOSED I O CONTROLLER CONNECTORS 11 SCREWS RETAINING THE MIB Figure 10 4 Rembving MI B 40 60 80 I 10 28 ...

Page 207: ...oward the mainframe until the board is close enough for the two internal ribbon cable paddle boards to be inserted in the appropriate connectors on the MIB 3 Insert both paddle boards L Position the HIB against the mainframe chassis so that the MIB retaining screws can be started in their holes NOTE Before fully tightening any of the MIB retaining screws be certain the NIB internal connectors are ...

Page 208: ... ribbon cables from tlleir connectors 3 Open the console panel and remove lall CPU and memory boards from the main frame 1 Remove the protective 5 Remove the chassis screws that hold the cmannel material 4 in place I remaining screws that fasten bar support 3 and the two HIB s to the mainframe 6 Carefully pull the basic MIB out away from the chassis just enough to expose the two interior ribbon ca...

Page 209: ...2 SUPPORT MIB INTERCONNECT CABLES SUPPORT SCREWS 3 1 0 CABLE CONNECTOR PROTECTIVE MATERIAL RETAINING SCREWS 4 AC LINE CORD GROMMET MIB INTERCONNECT CONNECTORS MIB EXPOSED DISCONNECT ___________________________ BOTH CABLES PULL OUT GROMMET MIB MIB EXTENSION Figure 10 5 Removing MI B s 45 65 85 10 31 ...

Page 210: ...s alignment can be examined froml the front of the chassis with the console panel open 5 Hhen the interior connectors are i b line with the board slots tighten the MIB retaining screws 6 Fasten the insulator panel channell able c6nnector in place 7 Return the CPU and memory boards Jo chassis I bar support and exterior I O bus their respective slots in the mainframe 8 Insert the external I O bus ca...

Page 211: ...terrupt Arm Clock Augend Bus Bits 00 through 15 Automatic Restart Bit Select Logic Bits 00 through 15 Bit Left Select Bit Right Select Carry Acknowledge Flip Flop D only Carry Acknowledge DMA Cable Console Interrupt Request Cold Start Serial Controller Clock 1 Serial Controller Clock 2 Clear Memory Data Register one Clear Memory Data Register Enable Clear Memory Data Register Left Clear Hemory Dat...

Page 212: ...ruction Pulse I D02 M Ory Start Enable e 1o r tI a Ck DOl or D03 DOl or D03 Data Port Enable DMA Ac lnoWledge DMA AcrnOWledge DMA Cable Data Bf S Bits 00 through 15 Serial I O Bit Clock 9 Serial I O Bit Clock 10 seriall I O Set Xmit Mode Device Control Pulse Serial I O Set Receive Mode Device Control Pulse Serial I O Set Echo Mode Device Control Pulse Serial I O Set Break Mode Device Control Pulse...

Page 213: ...t Enable DO Time 2 D02 Data Port Enable D02 Enable D02 Enable At D03 DO Time 3 D03 Data Port Enable DO Time I D04 Data Port Enable D04 Enable DO Clock I DO Clock I or 2 DO Clock I Data Port Enable DO Clock 2 DO Clock 3 DO Clock 4 DMA Operate on Memory DMA Cable DMA Priority Clock D02 DMA Cycle Steal Request DBA Cable Data Transfer In Data Transfer Out Data Transfer Pulse Data Transfer Pulse I O Ca...

Page 214: ...e XPO FunctJon Address Pulse Funct on Carry Into Adder C I n Function Inhibit to Adder Mode Control I Foreg1ound Mode Sel ct Function Select Lines to the ALU SO S3 I GEN Irtstruction Decode I GEN Instruction and S5 and D03 GEN Ii struction GEN S7 UCE GEN GEN GEN 2t ro Instruction Decode from IRS II o Load Byte Instruction Decode I oJ any Load LDA LDR LDBY Instruction Interf upt Request Levels 1 or...

Page 215: ...mory Inhibit Voltage I O Data Bits 00 through 15 I O Address 76 8 Decode from IRO 5 I O Address 77 8 Decode from IRO 5 I O Test Flip Flop Data Port Enable I O Test True Interrupt Priority Return Status Interrupt Priority Status Out Instruction Register Bits 00 through 15 Select IRO 3 or D 1AFO 3 to ALU Function Bus Interrupt Request I O Cable Interrupt Level Request 01 through 07 Interrupt System ...

Page 216: ...ort Enable I RLK orl ADDS Instruction Decode L Memi Ory Address Register Bits 00 through 11 Load ol Store All Registers and Status Instruc tion decode DMA M ltiPlex Address Control DMA Cable DMA M ltiPlex Address Control Flip Flop I HasteIj Clock I Maste Clock Oscillator Skip i nstruction Condition Met Memor Guard Multij lY Instruction Decode Multip ly Instruction at S9 MemorJ Reference Instructio...

Page 217: ...it N716 Not IR07 and IR06 IR07 0 IR06 1 N8l2 Not S8 and Sl and D02 N8l3 Not S8 and Sl and D03 N842 Not S8 and st and D02 N843 Not S8 and S4 and D03 N85l Not S8 and S5 and DOl N852 Not S8 and S5 and D02 N853 Not S8 and S5 and D03 N872 Not S8 and S7 and D02 N89 Not S8 and S9 N89l Not S8 and S9 and DOl N893 Not S8 and S9 and D03 Nll09 Not IRll and IR09 IRll 0 IR09 1 N8D02 Not S8 and D02 N8D03 Not S8 ...

Page 218: ...ow Indicator Clock Overflow Indicator Data Port overflbw Condition Het I Opera tl ions Honitor Alarm operat1 ions Monitor Powereb DOC3 Powerj d DOC4 Power ail Detect I Alarm Set Power IFail Interrupt Request Enable Power IFail or Restart Interrupt Request Power d GENI Power1d I Register Bits PowerJd ISE I Plus I ndlcator Plus ndicator Clock I Powered MTD1 I Powered N842 I Powerkd N852 I Power d Pu...

Page 219: ...eset Automatic Restart Flip Flop Reset Bit Instruction Decode Register Change Destination Instruction Class at SS and D03 Register Change Destination Instruction Class Enable Reset Console Interrupt Request Register Change Operate Instruction Class at SS and D03 Register Change Operate Instruction Class Enable Register Change Source Instruction Class at S5 and D03 Register Change Source Instructio...

Page 220: ...R Vector Address Register Operate Registl r Operate Readol 1Y Memory Literal Instruction Class Literal Instruction Class Enable DMA Request In at S8 Request Input DMA Cable I Rand Q Register Set Enable R Regi ter Bits 00 through 15 RO Rebor ROL Instruction Auto Rt start Group Decode I Register and St tus Counter Bits 1 2 4 8 Serial I O Read Start Real Td me Clock Real T me Clock Clock Real TI lme ...

Page 221: ...able Sl Set Enable Sequence State 2 S2 or S3 or S7 S2 Data Port Enable Sequence State 3 Indirect Addressing S3 Data Port Enable Sequence 5tate 4 S4 Data Port Enable Sequence State 5 S5 and S6 and S7 S5 Data Port Enable S5 or S6 S5 Register Destination Enable Sequence State 6 Micro Control S6 Data Port Enable Sequence 5tate 7 Interrupts S7 or S8 Sequence State 8 Data Channels Sequence State 9 Multi...

Page 222: ...r Save I IRegister Switch Set BiJ Left Set BiJ Right Shift Counter Bits 00 through 03 Shift I Count Complete Shift I Counter Clock I Shift Clock Serial Controller Select Console Switches to I O Bus serial lData Common selectr l for Decrement serial lData In serial l Data Out Memory Instruc tion select l Direct Memory Access serialr Controller Clock Control Set I Register Clock Set I f egister Enab...

Page 223: ...ion Select I Register Select Input Select I O Bus Select and Increment P Register Skip Instruction Decode Select E Register Select P Register Enable at D04 Select Source Register Select Memory Data Register Most Significant 6 Bits Selec t Memory r a ta Regis ter Bi ts 0 through 4 Select Memory Data Register Bit 9 Select Memory Data Register Bits 5 through 8 Select Memory Data Register and Extend B...

Page 224: ...or Circular Link Instrl ction Enable Shift Right Circular Link Shift ight Instruction SRI at S5 and D02 SRI a d S5 and D03 I Shift Right Logical or Arithmetic Instruction Enab11 Selecb R Register Left to Left Selecd R Register Left to Right selecJ R Register Right to Left selec d R Register Right selec J Register Source syste1 Reset Switch Select Status to Right for XIO Enable Store A Instruction ...

Page 225: ...egister Enable Set P Register Enable 1 Step Switch Set Q Register Enable Set Q Register Enable at DOC 2 Set Q Register Enable at DOC 4 Set R Register Enable Set R Register Enable At DOC 2 Set R Register Enable at DOC 4 Status Switch Set WRegister Enable Select WRegister Sync Pulse System Reset Select Indicators and Foreground Test Instruction Decode I O Test I O Cable Teletype Interrupt Turn Funct...

Page 226: ...t I Register Micro Select In Micro Select I O Input Micro Select M Register Bit 0 through 4 Micro Select H Register Bit 9 Micro elect M Register Bit 5 through 8 Micro jSelect M Register Extend Bit 8 Micro iselect M Register Extend Bit 9 Micro Select P Register Micro select Q Register Left to Left I Micro Select Q Register Right to Right Micro Select R Register Left to Left Micro Select R Register ...

Page 227: ...crement P Register Select W Register Bits 00 through 15 Memory Hrite Time Scratch Pad Write Clock Scratch Pad Hrite Enable Hait or Idle Hrite Set H and Set P Clock Enable Write Set Wand Set P Clock Transmit Data Serial I O Execute Instruction Decode XIO Instruction Decode Extended Processor Option Instructions MPY DIV Decode Extended Processor Option Flip Flop on from S5D03 through S9D02 XPO Link ...

Page 228: ...lect 2A 2B YS3A B Scratch Pad Register Y Drive Select 3A 3B YS4A B scratc Pad Register Y Drive Select 4A 4B ZACK Zero Acknowledge DMA Only ZCC ZACK al d CACK Flip Flop Clocks ZDET Zero Detect r l dicator ZERO Zero ZEROC Zero Fl iP Flop Clock Enable ZEROD Zero Data Port ZPLCE Zero l lllS and Link Clock Enable ZPOLS and Foreground Set InClicators ZRBY Zero Ri ight Byte Instruction Decode A 18 ...

Page 229: ...indicates that the components are not interchangeable Table B l SPC 16 40 Component Compatibility SPC 16 40 SPC 16 45 SPC 16 30 Assembly Series Series Series Number Part Type 40 60 80 45 65 85 30 50 70 31D01333A01 SPC 16 40 Arithmetic Board X X 0 X X 0 X X 0 31D01331A01 SPC 16 40 Macro Board X X X X X X X X X 31D01811All SPC 16 40 Timing Board X 0 0 X 0 0 X 0 0 31D01640A01 SPC 16 40 Processor MIB ...

Page 230: ... 0 0 0 0 0 31D01640All SPC 16 60 MIB I O Expansion Ix X X 31D01628A61 SPC 16 60 MIO Board Ix X 0 X X 0 31D01635A11 SPC 16 60 4K Memory Board I x X X I X X X X X X I 31D01594A51 SPC 16 60 8K Memory Board 0 X X 0 X X 0 0 0 31D01783AOl SPC 16 60 16K Memory Board X X X X X X 0 0 0 11COO025AOl SPC 16 60 Processor Chassis X X X 0 0 0 0 0 0 51DOO021AOl SPC 16 60 Power Supply I X X X X X X 0 0 0 31D01446A...

Page 231: ... 0 0 0 0 0 0 31D01640A11 SPC 16 80 MIB I O Expansion X X X 31D01628A71 SPC 16 80 MIO Board X X X X X X 31D01635A11 SPC 16 80 4K Memory Board X X X I X X X I X X X I 31D01594A31 SPC 16 80 8K Memory Board 0 0 X 0 0 X Q 0 0 31D01783A01 SPC 16 80 16K Memory Board X X X X X X 0 0 0 11COO025A01 SPC 16 80 Processor Chassis X X X 0 0 0 0 0 0 51DOO021AOl SPC 16 80 Power Supply X X X X X X 0 0 0 31D01446AOl...

Page 232: ...35All SPC 16 45 4K Memory Board X X X I X X X I X X X I I 31D01594A61 SPC 16 45 8K Memory Board X X X X X X 0 0 0 31D01783AOl SPC 16 45 16K Memory Board X X X X X X 0 0 0 llCOO026AOl SPC 16 45 Processor Chassis 0 0 0 X X X 0 0 0 51DOOO21AOI SPC 16 45 Power Supply X X X X X X 0 0 0 IlDOO036AOl SPC 16 45 Memory Expansion Chassis X X X 0 0 0 31D01650AOl SPC 16 45 Memory Expansion MIB X X X 0 0 0 31D0...

Page 233: ...11 SPC 16 65 4K Memory Board X X X X X X I X X X I 31D01594A51 SPC 16 65 8K Memory Board 0 X X 0 X X 0 0 0 31D01783A01 SPC 16 65 16K Memory Board X X X X X X 0 0 0 11COO026A01 SPC 16 65 Processor Chassis 0 0 0 X X X 0 0 0 51DOO021A01 SPC 16 65 Power Supply X X X X X X 0 0 0 11DOO036A01 SPC 16 65 Memory Expansion Chassis X X X 0 0 0 31D01650A01 SPC 16 65 Memory Expansion MIB X X X 0 0 0 31D01652A01...

Page 234: ...5All SPC l 6 85 4K Memory Board X X X X X X X X X I 31D01594A31 SPC 16 85 8K Memory Board 0 0 X 0 0 X 0 0 0 31D01783A01 SPC 16 85 16K Memory Board X X X X X X 0 0 0 11COO026AOl SPC 16 85 Processor Chassis 0 0 0 X X X 0 0 0 51DOO021AOl SPC 16 85 Power Supply X X X X X X 0 0 0 11DOO036AOl SPC 16 85 Memory Expansion Chassis I X X X 0 0 0 31D01650A01 SPC 16 85 Memory Expansion MIB X X X 0 0 0 31D01652...

Page 235: ...5 85 computer mainframes Tables C I through C 3 are parts lists for SPC 16 Models 40 60 and 80 respectively Tables C 4 through C 6 are parts lists for SPC 16 1odels45 65 and 85 respectively Table C 7 reflects 1IB Memory Module compatibility Table C 7 does not reflect any interchangeability between different speed CPU s C l ...

Page 236: ... Control Board w MULT DIV Macro Control Board w o FG BG or MULT DIV MIa Board Assembly wiTTY Controller MIB Assembly 4K Memory Boards only MIB Assembly I O Expansion MIB Assembly MIB Assembly Console Board Assy Console Assembly Chassis Ma nframe Computer Mainframe Assembly Model Numbers Notes Model 1640 0100 Model 1640 0200 Model 1640 0008 Model 1640 0004 Model 1640 0002 Model 1640 0001 72 Pin 56 ...

Page 237: ...B Assembly MIB Assembly MIBAssembly Console Board Assembly Console Assembly Chassis Mainframe Computer Mainframe Assy Size Features 4K x 16 8K x 16 16K x 16 w Fail Safe Group w F BG MULT DIV w F BG w MJLT DIV w o FG BG or MULTI DIV w TfY Controller I O Expansion 4K femory Boards Jnly Model Numbers Notes Model 1660 0100 Model 1660 0200 Model 1660 0008 Model 1660 0004 Model 1660 0001 72 Pin 56 Pin A...

Page 238: ... DIV Macro Control Board w FG BG Macro Control Board w MULT DIV Macro Control Board w o FG BG or MULT DIV MIO Board Assembly wiTTY Controller MIB Assembly 4K Memory Boards only MIB Assembly I O Expansion MIB Assembly MIB Assembly Console Board Assy Console Assembly Chassis Mainframe Computer Mainframe Assy I Model Numbers Notes Model 1680 0100 Model 1680 0200 Model 1680 0080 Model 1680 0004 Modei ...

Page 239: ...otes MIB Assembly Panel Dummy Exp MIB MIB Assembly Console Board Assy Arithmetic Board Macro Control Board Macro Control Board Macro Control Board Macro Control Board Timing Control Board Timing Control Board Chassis Mainframe Console Assembly Computer Mainframe Assy only Expanded Memory w FG BG MULTI DIV w FG BG w MULT DIV w o FG BG or MULTI I DIV w o Fail Safe Group w Fail Safe Group Model 1645 ...

Page 240: ...em Bds only MIB Assembly Panel Dummy Exp MIB MIB Assembly Expanded Memory Console Board Assy Arithmetic Board Macro Control Board w FG BG MULT DIV Model Macro Control Board w FG BG Model Macro Control Board w MULT DIV Macro Control Board w o FG BG or MULT DIV Timing Control Bbard w o Fail Safe Group Timing Control Bbard w Fail Safe Group Model Chassis Mainframe Console Assembly Model Computer Main...

Page 241: ...xp MIB MIB Assembly Expanded Memory Console Board Assy Arithmetic Board Macro Control Board w FG BG MULT DIV Macro Control Board w FG BG Macro Control Board w MULT DIV Macro Control Board w o FG BG or MULT DIV Timing Control Board w o Fail Safe Group Timing Control Board w Fail Safe Group Chassis Mainframe Console Assembly Computer Mainframe Assy I Model Numbers i Notes Model 1685 0100 Model 1685 ...

Page 242: ......

Page 243: ... indicate contents of the System Console Display register K register The K register is loaded under pro gram control by the DSPL instruction in the RUN mode in the IDLE mode it is loaded with the contents of the selected register see Register Select switches below REGISTER SELECT SWITCHES through These switches are used to select a register for display or data entry They have a left to right prior...

Page 244: ...ter select switch W Register select switch I Register select switch 16 DATA Entry switches ENTER switch SAVE I switch STEP switch RUN IDLE switch SYSTEMS RESET switch CONSOLE KEY LOCK 9 CONSOLE INTERRUPT switch FOREGROUND MODE indicator READ ONLY MEMORY ACCESS indicator DIRECT MEMORY ACCESS AUTOMATIC DATA CHANNEL ACKNOWLEDGE indicator INTERRUPT ACKNOWLEDGE indicator INTERRUPT ENABLE indicator OPER...

Page 245: ...n to be executed The program counter may be changed by setting the Data Entry switches j The interrupt status enable bit 15 is not affected when the program counter is changed o w REGISTER select switch displays the contents of the W register The W register contains the effective operand address for the last instruction executed The Working register may be changed by the Data Entry switches I REGI...

Page 246: ...talled shown by FOREGROUND MODE indicator and disables all lnterrupts CONSOLE ENABLE Key Lock This is a two position lock as follows CONSOLE DISABLED CONSOLE ENABLED Turning the key counterclockwise leaves the console disabled i e changing any of the console switches has no effect Turning clockwise will enable the console switches The console may be enabled disabled in either the RUN or IDLE mode ...

Page 247: ... being accessed for instructions or data DIRECT MEMORY ACCESS AUTOMATIC DATA CHANNEL ACKNOWLEDGE indicator indicates that a DMA cycle steal is taking place INTERRUPT ACKNOWLEDGE indicator indicates when an interrupt is being serviced Manually stepping through an interrupt will result in the address of the branch vector being displayed in the indicators Exit must be made by pressing STEP to execute...

Page 248: ......

Page 249: ...ruction AND 6 42 through 6 44 And Value with Register Instruction 6 44 through 6 47 Arithmetic Board 3 11 3 12 3 13 3 19 6 44 6 47 Arithmetic Logic Unit ALU 3 1 3 2 3 12 3 16 4 1 10 19 Arithmetic Operations 1 4 4 3 Assembly Drawing Numbers 3 13 10 2 Assembly Mainframe parts lists C 2 through C 7 Augend Bus See Bus Augend Automatic Restart 1 5 1 6 8 1 8 2 Background Mode 3 3 3 10 4 9 6 57 through 6...

Page 250: ...aintenance Corrective Maintenance Channel Address Register CAR 10 11 10 12 Circuit Rework 10 2 ClearM Register 6 9 Clock Counter TTY 3 23 Clocks 3 18 3 19 3 22 6 9 See aZso Master Clock DO Clock Combination Timing 3 16 3 17 3 18 3 19 5 9 5 10 Compare Memory with Register Instruction CMR 6 17 6 21 Complement Register Instruction CMPL 6 47 through 6 50 Component Interchangeability B 1 through B 6 16...

Page 251: ...itor Alarm PMA 6 57 through 6 61 Wai t WAIT 6 57 through 6 61 Control XIO Instruction CTRL 6 38 6 39 6 40 Controller Bbards 1 2 2 2 2 3 3 15 Controllers Connectors 3 15 Current Requirements 1 9 I O 1 5 Serial Teletype 3 22 3 23 10 4 Control Switches 3 10 Core Memory Operation 7 1 through 7 5 Corrective Maintenance Board Substitution 10 25 Data Channel 10 11 Data Transfer 10 12 through 10 24 Regist...

Page 252: ...10 12 through 10 24 Decrement Memory Instruction DECM 6 17 6 28 6 31 Decrement Register Instruction DECR 6 47 through 6 50 Diagnostic Programs 10 4 10 9 Digital to Analog Converter VU 3 10 Dimensions 1 6 Direct Memory Access Arithmetic Logic Control I O 1 5 5 12 Data Channel 1 5 10 11 10 12 Sequence States 6 70 Caution 6 51 DO Clock 5 2 Timing 3 19 3 20 5 12 See also Sequence States specific instr...

Page 253: ...ion 10 22 Foreground Background Modes 3 3 3 10 3 12 4 9 6 57 through 6 61 D 5 Foreground Indicator 3 6 D 5 Foreground Mode Set Instruction FMS 6 57 through 6 61 Function Bus Decoding 4 8 Function Select Signals 4 1 General Purpose Registers 3 3 3 4 3 12 4 9 4 10 Generate Sync Pulse Instruction SYNC 6 57 through 6 61 Hexadecimal Coding 10 3 Idle Mode 8 2 Increment Memory Instruction INCM 6 17 6 28 ...

Page 254: ...ansfer Rates 1 5 Installation Drawings 2 2 through 2 5 Instruction Execution Time 1 4 I Instructions Basic pecoding of 3 16 6 1 through 6 8 Instruction Set 1 4 3 9 6 1 through 6 9 Summary 6 2 through 6 9 Symbols and terms for 6 7 6 8 Interrupt Enable Instructions INE 6 57 through 6 61 Interrupt Inhibit Instruction INH 6 57 through 6 61 Interrupts 1 5 1 6 3 6 3 7 3 19 through 3 21 5 13 8 2 10 11 10...

Page 255: ... through 6 13 Load Value Into Register Instruction LDV 6 44 through 6 47 Logic Drawings 10 2 Logic Operations 4 4 L Register 3 6 3 7 3 21 3 22 Macro Control Board MAC 3 16 3 17 Mask 5 13 Mask Register Interrupt 3 20 Master Clock 3 18 5 2 6 9 10 11 See also specific instruction entry M aster Interconnect Board MIB Compatibility C 8 Connectors 3 14 3 15 Expansion 3 13 3 14 3 15 General 3 13 through ...

Page 256: ...6 Jump Unconditional JMP 6 10 J 6 16 Load Register A LDA 6 10 thfough 6 13 Store Register A STA 6 10 0 14 6 15 Memory Reference With Indexing Insi ruction Group MRX 6 3 6 17 through 6 36 I BIT Mode Instructions 6 17 6 22 6 24 6 26 6 27 6 28 BYTE Mode 6 17 6 22 through 25 Compare Memory to Register CMR 6 17 6 21 Decrement Memory DECM 6 17 6 28 6 31 Increment Memory INCM 6 17 6 28 6 31 Load All Regi...

Page 257: ...rough 6 44 Or Compare Value with Register Instruction ORVC 6 44 through 6 47 Or Regis t ers Instruction OR 6 42 through 6 44 Or Value with Register Instruction ORV 6 44 through 6 47 Paper Tape Bootstrap 10 7 through 10 9 Part Numbers C l through C 8 Pin Assignments 9 3 10 1 Positive Negative Saturation core 7 1 7 3 Potentiometers 9 4 9 5 Power Fail Automatic Restart 1 5 1 6 8 1 8 2 Timing of 5 13 ...

Page 258: ...struction 1RCSW 6 47 6 48 6 50 6 51 Read Console Switches Into Memory nstruction RCSM 6 3 8 6 40 through 6 42 Read Console Switches Into Registet Instruction RCSR 6 38 6 40 through 6 42 I Read Cycles 7 6 7 12 I Ready Only Memory ROM See Memory Read Only Register Add Link Instruction RLKj 6 47 through 6 50 Register Address Bus 3 20 Register Change Instruction Group 6 5 6 47 through 6 53 Add Shift C...

Page 259: ...pare Value to Register ADDVC 6 4 6 44 through 6 47 And Compare Value with Register ANDVC 6 4 6 44 through 6 47 Exclusive Or Compare Value with Register XORVC 6 4 6 44 through 6 47 Or Compare Value with Register ORVC 6 4 6 44 through 6 47 Subtract Compare Value from Register SUBVC 6 4 6 44 through 6 47 Register Operate Instruction Group 6 2 6 42 through 6 44 Add Registers ADD 6 2 6 42 through 6 44 ...

Page 260: ...so Foreground Background Registers Sense Ampli fiers Inhibit Drivers Sequence Advance Counter 5 10 Sequencing 6 9 general See Sequence St ates 3 19 5 2 5 6 instruct ion 1 12 7 13 also specific instruction th ough 5 9 6 9 6 70 Serial Cont roller I O Timing 5 12 Serial Optical Couplers 3 23 Set Bit I ns truction SBIT 6 17 6 22 6 24 6 26 6 27 Shift Instr uctions 3 5 6 5 6 531through 6 57 See also spe...

Page 261: ...l Registers and Status Instruction SARS 6 17 6 34 through 6 36 Store Byte Instruction STBY 6 17 6 22 6 24 6 25 Store Register Instruction STR 6 17 6 20 Store Register A Instruction STA 6 10 6 13 6 14 Subroutine Return Instruction RTRN 6 47 6 48 6 52 6 53 Subtract and Compare Registers Instruction SUBC 6 42 through 6 44 Subtract and Compare Value with Register Instruction SUBVC 6 44 through 6 47 Su...

Page 262: ...18 3 19 5 1 through 5 10 Serial Controller 5 12 Timing Control Board 10 20 3 18 through 3T20 5 2 5 9 7 12 10 9 through 10 11 Tools Test and Repair 10 12 I Transfer Regi ster to Status Instruction TRS I Transfer Stat us to Register Instruction TSR Voltage and Current Levels 8 1 Wait Condition 10 9 10 10 Wait Instruct ion WAIT 6 57 througt 6 61 W Register 3 8 3 12 W R Shift Register 3 8 X Y Current ...

Page 263: ... explain 00 you wish a reply Yes D No D COMMENTS Describe any errors suggested ideas additions or deletions etc Please include page number All comments and suggestions become the property of General Automation Inc No Postage Stamp Necessary If Mailed In the U S A See Other Side Fold On Dotted Lines And Staple ...

Page 264: ... for your use FOLD BUSINESS REPLY MAIL No Postage Necessary if Mailed in the United States Postage Will Be Paid By GENERAL AUTOMATION INC 1055 South East Street Anaheim California 92803 Attention Technical Publications General Automation Inc 1055 South East Street Anaheim California 92803 FOLD FI RST CLASS PERMIT NO 423 ANAHEIM CALIF I I I Iw z l i t Ig I J 1 I I I I I I I I I I I I I I I I I I I ...

Page 265: ......

Page 266: ...GENERALAUTOMATION INC 1055 South East Street Anaheim California 92805 714 778 4800 ...

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