Zynq UltraScale+, User Manual, Page: 17 / 70

RFSoC Data Converter Evaluation Tool User Guide 17
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Chapter 3: Hardware Design
Streaming MUX
The streaming MUX connects the incoming pattern to the selected channel(s) based on a
GUI command.
Figure 3-3 shows the stream data interface with AXIS FIFOs.
The TDATA is broadcast as is without any additional component in the path. This helps to
achieve timing closure because there is no multiplexer in the path.
The TVALID signal is ANDed with the Channel Control signal as shown in Figure 3-4 . Based
on user channel selection, the TVALID signal is enabled. The channel control select is
asserted based on mode (BRAM or DDR). For BRAM mode, it is controlled by software using
GPIOs. For DDR mode, it is controlled by a hardware logic block channel arbiter. The arbiter
block allocates the DMA access among the eight streaming interfaces based on number of
channels selected in the GUI. Software programs the Channel Select register based on the
GUI command. After the register is programmed, the arbiter block first samples the
predefined register to determine the active channels and arbitrates only among those
active channels in a round robin fashion (based on the TLAST on the streaming interface),
thereby effectively using the DDR bandwidth.
X-Ref Target - Figure 3-3
Figure 3-3: Stream Data Interface with AXIS FIFOs
Memory Loopback
0
Memory Loopback
1
------------
Memory Loopback
7
TDATA
X21235-090918
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