5-8
Z380
™
U
SER
'
S
M
ANUAL
DC-8297-03
Z
ILOG
5.5.2 16-Bit and 32-Bit Load, Exchange,
SWAP and PUSH/POP Group
(Continued)
Table 5-6. Supported Source and Destination Combination for 16-Bit and 32-Bit Load Instructions.
Source
Destination
BC
DE
HL
IX
IY
SP
nn
(nn)
(BC) (DE)
(HL)
(IX+d) (IY+d) (SP+d)
BC
L
L
L
L
L
IL
IL
L
L
L
IL
IL
IL
DE
L
L
L
L
L
IL
IL
L
L
L
IL
IL
IL
HL
L
L
L
L
L
IL
IL
L
L
L
IL
IL
IL
IX
L
L
L
L
IL
IL
L
L
L
IL
IL
IY
L
L
L
L
IL
IL
L
L
L
IL
IL
SP
L
L
L
IL
IL
(BC)
L
L
L
L
L
ILW
(DE)
L
L
L
L
L
ILW
(HL)
L
L
L
L
L
ILW
(nn)
IL
IL
IL
IL
IL
IL
(IX+d)
IL
IL
IL
IL
(IY+d)
IL
IL
IL
IL
(SP+d)
IL
IL
IL
IL
IL
Note:
The column with the character(s) are the allowed
source/destination combinations. The combination with
“L” means that the instruction is affected by Long Word
mode, “I” means that the instruction is can be used with
DDIR Immediate instruction. Also, “W” means the instruc-
tion uses the mnemonic of “LDW” instead of “LD”.
Table 5-7. Supported Operand for PUSH/POP Instructions
AF
BC
DE
HL
IX
IY
SR
nn
PUSH
√
√
√
√
√
√
√
√
POP
√
√
√
√
√
√
√
Note:
These PUSH/POP instructions are affected by Long Word mode of operations.
Various Z380 CPU registers are dedicated to specific
functions for these instructions—the BC register for a
counter, the DEz/DE and HLz/HL registers for memory
pointers, and the accumulator for holding the byte value
being sought. The repetitive forms of these instructions are
interruptible; this is essential since the repetition count can
be as high as 65536. The instruction can be interrupted
after any interaction, in which case the address of the
instruction itself, rather than next one, is saved on the
stack. The contents of the operand pointer registers, as
well as the repetition counter, are such that the instruction
can simply be reissued after returning from the interrupt
without any visible difference in the instruction execution.
In case of Word or Long Word block transfer instructions,
the counter value held in the BC register is decremented
by two or four, depending on the LW bit status. Since
exiting from these instructions will be done when counter
value gets to 0, the count value stored in the BC registers
5.5.3 Block Transfer and Search Group
This group of instructions (Table 5-8) supports block
transfer and string search functions. Using these instruc-
tions, a block of up to 65536 bytes of byte, Word, or Long
Word data can be moved in memory, or a byte string can
be searched until a given value is found. All the operations
can proceed through the data in either direction. Further-
more, the operations can be repeated automatically while
decrementing a length counter until it reaches zero, or they
can operate on one storage unit per execution with the
length counter decremented by one and the source and
destination pointer register properly adjusted. The latter
form is useful for implementing more complex operations
in software by adding other instructions within a loop
containing the block instructions.