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2
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7UGT U/CPWCN
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Interrupt Request (IREQ) Register Initialization
IREQ
(see Figure 4-6) is a register that stores the interrupt requests for both vectored and polled interrupts.
When an interrupt is issued, the corresponding bit position in the register is set to
1
. Bit
0
to bit
5
are assigned
to interrupt requests
IREQ0
to
IREQ5
, respectively.
Whenever RESET is executed, the
IREQ
resister is set to
00H
.
Figure 4-6. Interrupt Request Register.
Interrupt Request Register–IREQ (FAH)
Bit
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
R = Read W = Write X = Indeterminate U = Undefined/Undetermined
Bit
Position
R/W
Value
Description
7
R/W
0
Reserved,must be 0
6
R/W
0
1
IRQ6 reset
IRQ6 set
5
R/W
0
1
IRQ5 reset
IRQ5 set
4
R/W
0
1
IRQ4 reset
IRQ4 set
3
R/W
0
1
IRQ3 reset
IRQ3 set
2
R/W
0
1
IRQ2 reset
IRQ2 set
1
R/W
0
1
IRQ1 reset
IRQ1 set
0
R/W
0
1
IRQ0 reset
IRQ0 set