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Interrupt Mask Register (IMASK) Initialization

The 

IMASK

 register individually or globally enables or disables the interrupts (see Figure 4-4). When bits 

0

through bit 

6

 are set to 

1

, the corresponding interrupt requests are enabled. The 

IMASK2

 register, bits 0

through 7, enable and disable 

IRQ7

 through 

IRQ14

, respectively. Bit 

7

 is the master enable bit and must be

set before any of the individual interrupt requests can be recognized. Resetting bit 

7

 disables all the interrupt

requests. Bit 

7

 is set and reset by the 

EI

 and 

DI

 instructions. It is automatically set to 0 during an interrupt

service routine and set to 1 following the execution of an Interrupt Return (

IRET

) instruction. The 

IMASK

registers are reset to 

00H

, disabling all interrupts.

NOTE:

1.

It is not good programming practice to directly aqssign a value to the master enable bit. A value
change should always be accomplished by issuing the 

EI

 and 

DI

 instructions.

2.

Care should be taken not to set or clear 

IMASK

 bits while the master enable is set.

Summary of Contents for Z8 PLUS

Page 1: ...7 2 75 75 4 5 07...

Page 2: ......

Page 3: ...y ZiLOG accepts no liability for incidental or consequential damages arising from use of the software ZiLOG Inc shall not be responsible for any errors that may appear in this document ZiLOG Inc makes...

Page 4: ......

Page 5: ...y contain an instruction which appears as Click on File However an Index entry would appear as Grouping of Actions Within A Procedure Step Actions in a procedure step are all performed on the same win...

Page 6: ...XK 7 ADDITIONAL SOURCES OF INFORMATION In addition to this manual you should have access to and be familiar with the following documentation 0LFURFRQWUROOHUV 8VHU V 0DQXDO UM95Z800103 Data Sheet for e...

Page 7: ...egister Groups 1 6 Precautions 1 8 Control and Peripheral Registers 1 10 Control Registers 1 10 Peripheral Registers 1 10 Program Memory 1 11 Stack 1 13 Chapter 2 Addressing Modes Addressing Modes 2 1...

Page 8: ...ruction Description and Formats 3 19 ADC Add with Carry 3 20 ADC Add with Carry 3 22 ADD Add 3 23 AND Logical AND 3 25 CALL Call Procedure 3 27 CCF Complement Carry Flag 3 29 CLR Clear 3 30 COM Comple...

Page 9: ...urn 3 65 RL Rotate Left 3 66 RLC Rotate Left Through Carry 3 68 RLC Rotate Left Through Carry 3 69 RR Rotate Right 3 70 RRC Rotate Right Through Carry 3 72 RRC Rotate Right Through Carry 3 73 SBC Subt...

Page 10: ...Register Logic And Timing 4 4 Interrupt Mask Register IMASK Initialization 4 5 Interrupt Request IREQ Register Initialization 4 7 IREQ Software Interrupt Generation 4 9 Vectored Processing 4 9 Nestin...

Page 11: ...Addressing 2 2 Figure 2 2 4 Bit Register Addressing 2 3 Figure 2 3 Indirect Addressing of Register File Memory 2 4 Figure 2 4 Indirect Register Addressing to Program Memory 2 5 Figure 2 5 Indexed Regi...

Page 12: ...CPWCN KUV QH KIWTGU L 2 ZKK 7 Figure 4 6 Interrupt Request Register 4 7 Figure 4 7 Interrupt Request Register 2 4 8 Figure 4 8 Stacks Before and After Interrupt 4 10 Figure 4 9 Interrupt Vector Table...

Page 13: ...nstructions 3 3 Table 3 6 Block Transfer Instructions 3 3 Table 3 7 Rotate and Shift Instructions 3 4 Table 3 8 CPU Control Instructions 3 4 Table 3 9 Flag Definitions 3 7 Table 3 10 Flag Settings Def...

Page 14: ......

Page 15: ...ains both control registers and general purpose registers All the remaining pages pages 1 through 15 contain only general purpose registers Figure 1 1 illustrates the complete register file RAM space...

Page 16: ...7 Figure 1 1 Complete Register File RAM Space 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P A G E N U M B E R 255 128 127 0 Control Registers General Purpose Registers GPRs PAGES 1 THROUGH 15 CONTAIN GENERA...

Page 17: ...er Name Register Description Comments 0FFH STKPTR SPL Stack Pointer Low LSB of Stack Pointer 0FEH SPH Stack Pointer High MSB of Stack Pointer 0FDH REGPTR RP Register Pointer 0FCH FLAGS Flags 0FBH IMAS...

Page 18: ...to the next higher odd numbered register Figure 1 2 Table 1 2 Page 0 Register File Organization Hex Address Range Register Description F0 FF Core Control Registers E0 EF Virtual Copy of the Current Wo...

Page 19: ...n when defined as sources and read and or written when defined as destinations All General Purpose Registers function as accumulators address pointers index registers stack areas or scratch pad memory...

Page 20: ...ister is combined with the upper four bits High nibble of the Register Pointer thus forming the 8 bit actual address Figure 1 4 illustrates this operation Since working registers are typically specifi...

Page 21: ...4F 0011 3 30 3F 0010 2 20 2F 0001 1 10 1F 0000 0 00 0F Table 1 3 Working Register Groups Continued Register Pointer FDH High Nibble Binary Working Register Group HEX Actual Registers HEX 0 1 1 1 0 0...

Page 22: ...the port inputs and timer count registers may be updated by hardware Writing these registers from software always overrides the hardware update from the same cycle but with unpredictable results For...

Page 23: ...ent working register group There are no physical registers at that location Care must be taken that the Register Pointer never points at Group E on the first page be loaded with E0H This is an undefin...

Page 24: ...n addressable register Peripheral Registers Peripheral registers are used to transfer data configure the operating mode and control the operation of the on chip peripherals Any instruction that refere...

Page 25: ...bit vectors that corre spond to the available interrupts Address 0020H through the end of the populated memory 0FFFFh 64 KB maximum consists of on chip mask programmable ROM or EPROM or Flash The fir...

Page 26: ...f Instruction Executed After RESET IRQ6 IRQ14 On chip ROM or Decimal Address 65535 33 32 31 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 PC Rollover Vector JR Instruction PC Rollov...

Page 27: ...prior to a PUSH operation and incremented after a POP operation The stack address always points to the data stored on the top of the stack The stack is a return stack for CALL instruc tions and inter...

Page 28: ...5RCEG L 2 7 Figure 1 8 Stack Operations PCL Top of Stack Stack Contents PCH PCL PCH FLAGS After an Interrupt Cycle Stack Contents After a Call Instruction Top of Stack Prior value of Stack Pointer Pri...

Page 29: ...age by specifying an 8 bit address The upper 4 bits of the absolute address is specified by pre pending the lower 4 bits of the Register Pointer 0FDH the Page Pointer to the 8 bit address to form a 12...

Page 30: ...ailable REGISTER ADDRESSING R In 8 bit Register Addressing mode the operand value is equivalent to the contents of the specified register or register pair In the Register Addressing see Figure 2 1 the...

Page 31: ...he Indirect Register Addressing Mode the contents of the specified register are equivalent to the address of the operand see Figure 2 3 and Figure 2 4 Depending upon the instruction selected the speci...

Page 32: ...Memory OpCode One Operand Register File Operand Program Memory Points to One 8 Bit Register Value Used in Address of the Operand Instruction Example File Address Address dst Points to the Register of...

Page 33: ...he Index This offset is added to the register address to obtain the address of the operand Figure 2 5 illustrates this addressing convention OpCode Instruction Example Program Register File Program Me...

Page 34: ...5 Indexed Register Addressing OpCode Register File Program Memory Points to the src Two Operand Points to the Origin Instruction dst RP Operand Offset Working Register Offset Address of Working Regist...

Page 35: ...mode as shown in Figure 2 6 specifies the address of the next instruction to be executed Only the Conditional Jump JP and Call CALL instructions use this addressing mode Figure 2 6 Direct Addressing...

Page 36: ...nts of the Program Counter to obtain the address of the next instruction to be executed The PC prior to the add consists of the address of the instruction following the Jump Relative JR or Decrement a...

Page 37: ...essing mode that does not indicate a register or memory address as the source operand The operand value used by the instruction is the value supplied in the operand field itself Because an immediate o...

Page 38: ......

Page 39: ...d Shift CPU Control Table 3 1 through Table 3 8 show the instructions belonging to each group and the number of operands required for each The source operand is src the destination operand is dst and...

Page 40: ...s Mnemonic Operands Instruction ADC dst src Add with Carry ADD dst src Add CP dst src Compare DA dst Decimal Adjust DEC dst Decrement DECW dst Decrement Word INC dst Increment INCW dst Increment Word...

Page 41: ...nterrupt Return JP cc dst Jump JR cc dst Jump Relative RET Return Table 3 5 Bit Manipulation Instructions Mnemonic Operands Instruction TCM dst src Test Complement Under Mask TM dst src Test Under Mas...

Page 42: ...RR dst Rotate Right RRC dst Rotate Right Through Carry SRA dst Shift Right Arithmetic SWAP dst Swap Nibbles Table 3 8 CPU Control Instructions Mnemonic Operands Instruction CCF Complement Carry Flag D...

Page 43: ...signed a value Figure 3 1 Flag Register Flag Register FCH Read Write R252 Flags Bit 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W R W Reset U U U U U U R Read W Write X Indeterminate U Unchanged Bit...

Page 44: ...ccurs Following logical operations the Overflow Flag is cleared to 0 The Overflow Flag is not effected by RESET Decimal Adjust Flag D 3 R W The Decimal Adjust Flag is used for BCD arithmetic Since the...

Page 45: ...o determine if a RESET occurred if a WDT timeout occurred or if a return from STOP mode occurred Software must explicitly clear this flag after detecting the timeout condition Failure to clear this fl...

Page 46: ...according to operation Unaffected X Undefined Table 3 11 Condition Codes Binary HEX Mnemonic Definition Flag Settings 0000 0 F Always False 1000 8 blank Always True 0111 7 C Carry C 1 1111 F NC No Car...

Page 47: ...XOR V 1 1010 A GT Greater Than Z OR S XOR V 0 0010 2 LE Less Than or Equal Z OR S XOR V 1 1111 F UGE Unsigned Greater Than or Equal C 0 0111 7 ULT Unsigned Less Than C 1 1011 B UGT Unsigned Greater T...

Page 48: ...ter or Indirect Working Register Reg Rn Reg represents a number in the range of 00H to FFH n 0 15 Irr Indirect Working Register Pair RRp p 0 2 4 6 8 10 12 or 14 IRR Indirect Register Pair or Working R...

Page 49: ...ctions operate with several addressing modes This situation is indicated by an op code number written like x The brackets are filled by a nibble indicating the addressing mode in use For example ADD 0...

Page 50: ...r is used and an 8 bit address is required by the assembler an E is pre pended to the 4 bit working register address If in the above example the source register is a working register the assembly synt...

Page 51: ...c C Z S V D H ADC dst src dst dst src C 1 0 ADD dst src dst dst src 0 0 AND dst src dst dst AND src 5 0 CALL src SP SP 2 PC src DA D6 CALL src SP SP 2 PC src IRR D4 CCF C NOT C EF CLR dst dst 0 R IR B...

Page 52: ...f dst 0 then PC PC src Range 128 src 127 RA rA r 0 F EI IMR 7 1 9F HALT 7F INC dst dst dst 1 r R IR rE r 0 F 20 21 INCW dst dst dst 1 RR IR A0 A1 IRET FLAGS SP SP SP 1 PC SP SP SP 2 IMR 7 1 BF JP cc s...

Page 53: ...Im R r X r Ir r R IR IM IM R r C r 8 r 9 r 0 F C7 D7 E3 F3 E4 E5 E6 E7 F5 LDC dst src dst src r lrr Irr r C2 D2 LDCI dst src dst src dst dst 1 src src 1 Ir lrr Irr r C3 D3 NOP FF OR dst src dst dst OR...

Page 54: ...RR dst R IR E0 E1 RRC dst R IR C0 C1 SBC dst src dst dst src C 3 1 SCF C 1 DF 1 SRA dst R IR D0 D1 0 SRP src RP src Im 31 STOP 6F SUB dst src dst dst src 2 1 SWAP dst R IR F0 F1 TCM dst src NOT dst A...

Page 55: ...75 7UGT U CPWCN L 2 PUVTWEVKQP 5GV 7 Figure 3 2 which follows illustrates the Op Code map Table 3 15 Lower Nibble Values Address Mode dst src Lower op code Nibble r r 2 r Ir 3 R R 4 R IR 5 R IM 6 IR I...

Page 56: ...R1 IM STOP 7 PUSH R2 PUSH IR2 TM r1 r2 TM r1 Ir2 TM R2 R1 TM IR2 R1 TM R1 IM TM IR1 IM HALT 8 DECW RR1 DECW IR1 DI 9 RL R1 RL IR1 EI A INCW RR1 INCW IR1 CP r1 r2 CP r1 Ir2 CP R2 R1 CP IR2 R1 CP R1 IM...

Page 57: ...orking register In this format the source or destina tion working register operand is specified by adding 1110B EH to the High nibble of the operand For example if working register R12 CH is the desti...

Page 58: ...operands to be carried into the addition of high order operands Flags When the instruction is executed the flags are set as follows C 1 if a value is carried from the most signigicant bit of the resu...

Page 59: ...ollowing statements leave the value 27H in working register R16 the C Z S V D and H flags are set to 0 ADC R16 R10 Op Code 13 FA Example Register 34H contains 2EH The C flag is set Register 12H contai...

Page 60: ...g statement leaves the value 2DH in register 6CH The C Z S V D and H flags are set to 0 ADC 6CH 03H Op Code 16 6C 03 Example Register D4H contains 5FH Register 5FH contains 4CH The C flag is set The f...

Page 61: ...the flags are set as follows C 1 if a value is carried from the most significant bit of the result otherwise 0 Z 1et if the result is 0 otherwise 0 S 1 if the result is negative otherwise 0 V 1 if an...

Page 62: ...The following statement leaves the value 49H in register 34H The H flag is set to 1 and the C Z S V and D flags are set to 0 ADD 34H 12H Op Code 04 12 34 Example Register 4BH contains 82H Working reg...

Page 63: ...the instruction is executed the flags are set as follows Example Working register R1 contains 34H 00111000B and working register R14 contains 4DH 10001101 The following statement leaves the value 04H...

Page 64: ...eared AND 3AH 42H Op Code 54 42 3A Example If working register R5 contains F0H 11110000B Register 45H contains 3AH Register 3AH contains 7FH 01111111B The following statement leaves the value 70H 0111...

Page 65: ...nstruction of the procedure At the end of the procedure a return RET instruction can be used to return to the original program flow RET pops the top of the Stack and replaces the original value into t...

Page 66: ...521H and now points to the address of the first statement in the procedure to be executed CALL 3521H Op Code D6 35 21 Example The contents of the PC are 1A47H The contents of the SP register FFH are 7...

Page 67: ...d the flags are set as follows Example The C flag contains a 0 The following statement changes the C flag from C 0 to C 1 CCF Op Code EF C The value set by the preceding instruction is complemented Z...

Page 68: ...R6 CLR R6 Op Code B0 E6 Example Register A5H contains the value 23H Register 23H contains the value FCH The following state ment leaves the value 00H in register 23H CLR A5H Op Code B1 A5 C The value...

Page 69: ...BH 11011011 in register 08H The S flag is set to 1 and the Z and V flags are set to 0 COM 08 Op Code 60 08 Example Register 08H contains 24H and register 24H contains FFH 11111111B The following state...

Page 70: ...he instruction is executed the flags are set as follows C 1 if a value is carried from the most significant bit of the result otherwise 0 Z 1 if the result is 0 otherwise 0 S 1 if bit 7 of the result...

Page 71: ...contains 2EH Register 12H contains 1BH The following statement sets the C Z S and V flags to 0 CP 34H 12H Op Code A4 12 34 Example Register 4BH contains 82H Working register R3 contains 10H Register 1...

Page 72: ...raction of BCD digits the result is meaningless Table 3 16 DA Operation Reference Prior Instruction Flags Before DA Result Before Adjustment Added Result After C Flag After C H D 7 4 3 0 7 4 3 0 ADD o...

Page 73: ...s stored in Register 5FH the following statement adjusts this result so the correct BCD representation is obtained DA 5FH Op Code 41 45 Register 5F now contains the value 42H The C Z and S flags are s...

Page 74: ...performed on the binary representations of the BCD numbers Register 45H contains the value 5FH The result of the subtraction is stored in 5FH The following statements adjust the result so the correct...

Page 75: ...flags are set to 0 DEC R10 Op Code 00 EA Example Register B3H contains CBH Register CBH contains 01H The following statement leaves the value 00H in Register CBH The Z flag is set to 1 and the V and S...

Page 76: ...n register pair 30H and 31H The Z V and S flags are set to 0 DECW 30H Op Code 80 30 Example Working register R0 contains 30H Register Pair 30H and 31H contain the value FAF3H The following statement l...

Page 77: ...When the instruction is executed the flags are set as follows Example Control register FBH contains 8AH 10001010B interrupts IRQ1 and IRQ3 are enabled The following statement sets control register FB...

Page 78: ...register counter reaches 0 control falls through to the statement following the DJNZ instruction Flags When the instruction is executed the flags are set as follows Example DJNZ is typically used to c...

Page 79: ...CN L 2 FFTGUU 5RCEG 7 DJNZ Decrement And Jump If Non zero The assembly listing required for this routine is as follows Assembly Op Code LD R6 12 6E 0C LOOP LD R9 20 R6 C7 56 30 LD 14 R6 R9 D7 56 10 DJ...

Page 80: ...as follows Example Control Register FBH contains 0AH 00001010 interrupts IRQ1 and IRQ3 are selected The following statement sets Control Register FBH to 8AH 10001010B enabling IRQ1 and IRQ3 EI Op Cod...

Page 81: ...e flags are set as follows Example Assuming the Z8 is in normal operation the following statements place the Z8 into HALT mode HALT Op Codes 7F NOTE Unlike the Z8 the Z8PLUS does not require a NOP bef...

Page 82: ...ruction is executed the flags are set as follows C The value set by the preceding instruction Z 1 if the result is 0 otherwise 0 S 1 if bit 7 of the result is 1 negative otherwise 0 V 1 if arithmetic...

Page 83: ...INC R10 Op Code AE Example Register B3H contains CBH The following statement leaves the value CCH in register CBH The S flag is set to 1 and the Z and V flags are set to 0 INC B3H Op Code 20 B3 Examp...

Page 84: ...3H in register pair 30H and 31H The Z V and S flags are set to 0 INCW 30H Op Code A0 30 Example Working register R0 contains 30H Register pairs 30H and 31H contain the value FAF3H The following statem...

Page 85: ...e 45H Register 45H contains the value 00H Register 46H contains 6FH Register 47 Contains E4H The following statement restores the Flags Register FCH with the value 00H restores the PC with the value 6...

Page 86: ...al jump simply replaces the contents of the Program Counter with the contents of the register pair specified by the destination operand Program Control then passes to the instruction addressed by the...

Page 87: ...am control to that location If the Carry flag had not been 1 control would have fallen through to the statement following the JP instruction JP C 1520H Op Code 7D 15 20 Example Working register pair R...

Page 88: ...d the flags are set as follows Example The result of the last arithmetic operation executed is negative The next nine bytes are skipped with the following statement If the result is not negative execu...

Page 89: ...dst OPC dst src OPC src dst OPC dst X src OPC src X dst For OPC r9H only a full 8 bit register can be used The L 2 assember automatically uses the r8 Op Code for an instruction like LD R0 R1 OPC Hex A...

Page 90: ...Op Code F8 34 Example Working register R14 contains the value 45H The following statement loads the value 45H into register 34H The contents of working register R14 are not changed LD 34H R14 Op Code...

Page 91: ...r 34H The contents of register 45H are not changed LD 34H 45H Op Code E4 45 34 Example Register 45H contains the value CFH Register CFH contains the value FFH The following state ment loads the value...

Page 92: ...contains the value 4FH The following statement loads working register R10 with the value 4FH The contents of working register R0 and Register 2CH are not changed LD R10 24H R0 Op Code C7 A0 24 Example...

Page 93: ...le Working register pairs R6 and R7 contain the value 30A2H and program memory location 30A2H contains the value 22H The following statement loads the value 22H into working register R2 The value of p...

Page 94: ...Working register pair R6 and R7 contains the value 10A2H The following statement loads the value 22H into program memory location 10A2H The value of working register R2 is unchanged by the load LDC R...

Page 95: ...nts of the source location are loaded into the destination location Both addresses in the working registers are then incremented automatically The contents of the source operand are not changed Flags...

Page 96: ...er 21H working register pair RR6 is incremented to 30A4H and working register R2 is incremented to 22H LDCI R2 RR6 Op Code C3 26 Example Working register R2 contains 20H Register 20H contains 22H Regi...

Page 97: ...learing the pipeline Flags When the instruction is executed the flags are set as follows C The value set by the preceding instruction Z The value set by the preceding instruction S The value set by th...

Page 98: ...1 bit whenever either of the corresponding bits in the two operands is a 1 Otherwise a 0 bit is stored Flags When the instruction is executed the flags are set as follows C The value set by the prece...

Page 99: ...value 0AH 00001010B The following statement leaves the value FFH 11111111B in register 3AH The S flag is setto 1 and the Z and V flags are set to 0 OR 3AH 42H Op Code 44 42 3A Example Working register...

Page 100: ...s 71H The contents of register 70 are not changed POP 34H Op Code 50 34 Example The SP Control Registers FEH and FFH contains the value 1000H Memory location 1000H contains 55H Working register R6 con...

Page 101: ...FCH the Flag Register in location 1000H After the PUSH operation the SP contains 1000H PUSH FCH Op Code 70 FC Example The SP contains 61H Working register R4 contains FCH The following statement store...

Page 102: ...ecuted the flags are set as follows Example The C flag is currently set to 1 The following statement resets the Carry flag to 0 RCF Op Code CF C 0 Z The value set by the preceding instruction S The va...

Page 103: ...untered with a POP instruction in order to guarantee the SP is at the correct location when the RET instruction is executed Otherwise the wrong address is loaded into the PC and the program does not o...

Page 104: ...he Carry flag Flags When the instruction is executed the flags are set as follows C 1 if the bit rotated from the most significant bit position was 1 that is bit 7 was previously set to 1 Z 1 if the r...

Page 105: ...0001B in register C6H The C and V flags are setto 1 and the S and Z flags are set to 0 RL C6H Op Code 80 C6 Example The contents of register C6H are 88H The contents of register 88H are 44H 01000100B...

Page 106: ...3 dst 2 dst 4 dst 3 dst 5 dst 4 dst 6 dst 5 dst 7 dst 6 The contents of the destination operand along with the C flag are rotated left by one bit position The initial value of bit 7 becomes the value...

Page 107: ...ter R4 contains C6H Register C6 contains 8F 10001111B The following statement leaves register C6 with the value 1EH 00011110B The C and V flags are set to 1 and S and Z flags are set to 0 RLC R4 Op Co...

Page 108: ...ue of bit 7 and the C flag Flags When the instruction is executed the flags are set as follows C 1 if the value rotated from the least significant bit position bit 1 was 1 Z 1 if the result is 0 other...

Page 109: ...s the value 98H 10011000B in working register R6 The C V and S flags are set to 1 and the Z flag is set to 0 RR R6 Op Code E0 E6 Example The contents of register C6 are 31H The contents of register 31...

Page 110: ...2 dst 2 dst 3 dst 3 dst 4 dst 4 dst 5 dst 5 dst 6 dst 6 dst 7 dst 7 C The contents of the destination operand with the C flag are rotated right by one bit position The value of the C flag becomes the...

Page 111: ...ts of register 2C are EDH The contents of register EDH is 02H 00000010B The C flag is 0 The following statement leaves the value 01H 00000001B in register EDH The C Z S and V flags are reset to 0 RRC...

Page 112: ...ow order operands to be subtracted from the subtraction of high order operands Flags When the instruction is executed the flags are set as follows C 0 if a value is carried from the most significant b...

Page 113: ...ontains 1BH The following statement leaves the value 12H in register 34H The D flag is set and the C Z S V and H flags are cleared SBC 34H 12H Op Code 34 12 34 Example Register 4BH contains 82H The C...

Page 114: ...executed the flags are set as follows Example The C flag is currently 0 The following statement sets the Carry flag to 1 SCF Op Code DF C 1 Z The value set by the preceding instruction S The value set...

Page 115: ...bit is unchanged Bit 6 becomes the same as the value of bit 7 The result is a signed divide by two holding the half bit remainder stored in the Carry C flag Flags When the instruction is executed the...

Page 116: ...lue 98H 00011000B in working register R6 The C flag is set to 1 and the Z V and S flags are set to 0 SRA R6 Op Code D0 E6 Example Register C6 contains the value DFH Register DFH contains the value B8H...

Page 117: ...ory pages results in undefined behavior Table 3 17 Register Pointers Working Register Groups and Actual Registers Register Pointer FDH Contents Bin Working Register Group Hex Actual Registers Hex 1111...

Page 118: ...efore accessable as R0 through R15 in four bit addressing modes The active memory page is set to page 0 and all eight bit addressed register accesses are on page 0 SRP 70 Op Code 31 F0 C The value set...

Page 119: ...the FLAGS register specifically the SMR and WDT flags see page 3 5 for more information Flags When the instruction is executed the flags are set as follows Example The following statements place the...

Page 120: ...s executed the flags are set as follows C 0 if a value is carried from the most significant bit of the result otherwise 1 indicating a borrow Z 1 if the result is 0 otherwise 0 V 1 if arithmetic overf...

Page 121: ...The following statement leaves the value 13H in register 34H The D flag is set to 1 and the C Z S V and H flags are set to 0 SUB 34H 12H Op Code 24 12 34 Example Register 4BH contains 82H Working reg...

Page 122: ...register BCH The Z and S flags are set to 0 SWAP B3H Op Code F0 B3 Example Working register R5 contains BCH and register BCH contains B3H 10110011B The following statement leaves the value 3BH 0011101...

Page 123: ...he TCM operation is complete the destination and source operands still contain their previous values Flags When the instruction is executed the flags are set as follows Example Working register R3 con...

Page 124: ...e 64 E0 D4 Example Register DFH contains the value FFH 11111111B Register 07H contains the value 1FH Register 1FH contains the value BDH 10111101B bit 7 bit 5 bit 4 bit 3 bit 2 and bit 0 are tested if...

Page 125: ...i nation and source operands still contain their previous values Flags When the instruction is executed the flags are set as follows Example Working register R3 contains 45H 01000101B Working register...

Page 126: ...r DFH contains the value 00H 00000000B Register 07H contains the value 1FH Register 1FH contains the value BDH 10111101B bit 7 bit 5 bit 4 bit 3 bit 2 and bit 0 are tested if they are 0 The following...

Page 127: ...s the WDT from timing out Flags When the instruction is executed the flags are set as follows Example The WDT is enabled The following statement refreshes the Watch Dog Timer WDT Op Code 5F C The valu...

Page 128: ...ination operand is set to 1 otherwise a 0 is stored The contents of the source operand are not changed Flags When the instruction is executed the flags are set as follows C The value set by the preced...

Page 129: ...ntains the value 0AH 00001010B The following statement leaves the value FFH 11111111B in register 3AH The S flag is set to 1 and the C and V flags are set to 0 XOR 3AH 42H Op Code B4 42 3A Example Wor...

Page 130: ......

Page 131: ...are globally enabled by setting bit 7 to 1 with an Enable Interrupt EI instruction There are four interrupt control registers the Interrupt Request Registers IREQ and IREQ2 and the Inter rupt Mask re...

Page 132: ...Diagram NOTE See the selected Z8PLUS MCU s product specification for the exact interrupt sources supported 0FBH 0FAH IMASK IREQ 0F9H 0F8H IMASK2 IREQ2 Interrupt Mask Interrupt Request Interrupt Mask...

Page 133: ...dge options and exact programming details 2 Although interrupts are edge triggered minimum interrupt request Low and High times must be observed for proper operation See the device product specificati...

Page 134: ...retired the Z8PLUS core does not execute an instruction during the next instruction cycle The Z8PLUS MCU instead selects the highest priority outstanding interrupt to be serviced The program counter...

Page 135: ...ividual interrupt requests can be recognized Resetting bit 7 disables all the interrupt requests Bit 7 is set and reset by the EI and DI instructions It is automatically set to 0 during an interrupt s...

Page 136: ...0 0 0 0 R Read W Write X Indeterminate U Undefined Undetermined Bit Position R W Value Description 7 0 1 Disables Interrupts Enables Interrupts 6 0 1 Disables IRQ5 Enables IRQ5 5 0 1 Disables IRQ5 Ena...

Page 137: ...d W Write X Indeterminate U Undefined Undetermined Bit Position R W Value Description 7 R W 0 1 Disables IRQ14 Enables IRQ14 6 R W 0 1 Disables IRQ13 Enables IRQ13 5 R W 0 1 Disables IRQ12 Enables IRQ...

Page 138: ...ectively Whenever RESET is executed the IREQ resister is set to 00H Figure 4 6 Interrupt Request Register Interrupt Request Register IREQ FAH Bit 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W R W Re...

Page 139: ...R W Reset 0 0 0 0 0 0 0 0 R Read W Write X Indeterminate U Undefined Undetermined Bit Position R W Value Description 7 R W 0 IRQ14 reset IRQ14 set 6 R W 0 1 IRQ13 reset IRQ13 set 5 R W 0 1 IRQ12 rese...

Page 140: ...ransferred to the service routine pointed to by the IREQ5 vector NOTE Note that software may modify the IREQ register at any time Care should be taken when using any instruction that modifies the IREQ...

Page 141: ...L 2 PVGTTWRVU 7 Figure 4 8 Stacks Before and After Interrupt SP Old Top of Stack PC LOW Byte PC HIGH Byte FLAGS Stack Pointer and Stack SP 3 Stack Pointer and Stack Top of Stack After an Interrupt Be...

Page 142: ...he old IMASK on the stack Load IMASK with a new mask to disable lower priority interrupts Execute an EI instruction Proceed with interrupt processing Execute a DI instruction after processing is compl...

Page 143: ...branch to the service routine The service routine services the request resets its Request Bit in the IREQ and branches or returns back to the main program An example of a polling routine is as follow...

Page 144: ......

Page 145: ...ts speeds up to 28 8K Baud with connections 8 N 1 8 bits No parity 1 stop bit We recommend that you use an ANSI BBS terminal emula tion setup To preview information or download files follow the on scr...

Page 146: ......

Page 147: ...occurrence of the problem Attach additional pages as necessary ______________________________________________________________________________________ _________________________________________________...

Page 148: ......

Page 149: ...manipulation instructions bit clear AND 3 3 bit complement XOR 3 3 bit set OR 3 3 test complement under mask TCM 3 3 3 85 test under mask TM 3 3 3 87 block diagram interrupt 4 2 C call procedure CALL...

Page 150: ...zero 3 5 G general purpose registers 1 5 H half carry flag H 3 6 halt HALT 3 43 high nibble 1 6 I immediate data addressing IM 2 9 increment INC 3 44 increment word INCW 3 46 indexed addressing X 2 5...

Page 151: ...rand destination 3 1 dst 3 1 source 3 1 src 3 1 overflow flag 3 6 P peripheral registers 1 10 polled interrupt 4 2 pop POP 3 62 processor flags 3 5 program control inctructions IRET instruction 3 47 p...

Page 152: ...A 3 77 shorthand notational 3 10 sign flag S 3 6 source operand src 3 1 stack pointer register SP 1 13 stop STOP 3 81 stop mode recovery flag SMR 3 7 subtract SUB 3 82 subtract with carry SBC 3 74 swa...

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