ZiLOG Z08617 Manual Download Page 22 | Manualshive

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Z08617 NMOS Z8

®

8-B

IT

MCU

K

EYBOARD

C

ONTROLLER

22

INSTRUCTION SUMMARY

(Continued)

Address

Flags

Instruction

Mode

Opcode

Affected

and Operation

dst src

Byte (Hex) C Z S V D H

ADC

dst, src

†

1[

]

✻ ✻ ✻ ✻

0

✻

dst

←

dst + src + C

ADD

dst, src

†

0[

]

✻ ✻ ✻ ✻

0

✻

dst

←

dst + src

AND

dst, src

†

5[

]

✻ ✻

0

–

–

dst

←

dst AND src

CALL

dst

DA

D6

–

–

–

–

–

–

SP

←

SP – 2

IRR

D4

@SP

←

PC,

PC

←

dst

CCF

EF

✻

–

–

–

–

–

C

←

NOT C

CLR

dst

R

B0

–

–

–

–

–

–

dst

←

0

IR

B1

COM

dst

R

6 0

–

✻ ✻

0

–

–

dst

←

NOT dst

IR

6 1

CP

dst, src

†

A[

]

✻ ✻ ✻ ✻

–

–

dst –

src

DA

dst

R

4 0

✻ ✻ ✻

X –

–

dst

←

DA dst

IR

4 1

DEC

dst

R

0 0

–

✻ ✻ ✻

–

–

dst

←

dst – 1

IR

0 1

DECW

dst

RR

8 0

–

✻ ✻ ✻

–

–

dst

←

dst – 1

IR

8 1

DI

8 F

–

–

–

–

–

–

IMR(7)

←

0

DJNZ

r, dst

RA

r A

–

–

–

–

–

–

r

←

r – 1

r = 0 – F

if r

≠

0

PC

←

PC + dst

Range: +127,–128

EI

9 F

–

–

–

–

–

–

IMR(7)

←

1

Address

Flags

Instruction

Mode

Opcode

Affected

and Operation

dst src

Byte (Hex) C Z S V D H

INC

dst

r

rE

–

✻ ✻ ✻

–

–

dst

←

dst + 1

r = 0 – F

R

2 0

IR

2 1

INCW

dst

RR

A 0

–

✻ ✻ ✻

–

–

dst

←

dst + 1

IR

A 1

IRET

BF

✻ ✻ ✻ ✻ ✻ ✻

FLAGS

←

@SP;

SP

←

SP + 1

PC

←

@SP;

SP

←

SP + 2;

IMR(7)

←

1

JP

cc, dst

DA

CD

–

–

–

–

–

–

if cc is true

C = 0 – F

PC

←

dst

IRR

3 0

JR

cc, dst

RA

CB

–

–

–

–

–

–

if cc is true,

C = 0 – F

PC

←

PC + dst

Range: +127,–128

LD

dst, src

r

Im

rC

–

–

–

–

–

–

dst

←

src

r

R

r 8

R

r

r 9
r = 0 – F

r

X

C7

X

r

D7

r

Ir

E3

Ir

r

F 3

R

R

E4

R

IR

E5

R

IM

E6

IR

IM

E7

IR

R

F 5

LDC

dst, src

r

Irr

C2

–

–

–

–

–

–

LDCI

dst, src

Ir

Irr

C3

–

–

–

–

–

–

dst

←

src

r

←

r + 1;

rr

←

rr + 1

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Summary of Contents for Z08617

Page 1: ...O scheme an efficient register I O and a number of ancillary features that are useful in many industrial and advanced scientific applications For applications which demand powerful I O capabili ties the Z08617 provides 32 pins dedicated to input and output These lines are grouped into four ports each port consists of 8 lines and are configurable under software control to provide timing status sign...

Page 2: ...Bit Programmable ALU Flags Register Pointer Register File 124 x 8 Bit Machine Timing Instruction Control Program Memory Program Counter Vcc GND Output Input Port 0 Port 1 I O Output Open Drain Nibble Programmable I O Output Open Drain Byte Programmable 4 4 8 WDT POR WDTOUT RESET XTAL2 XTAL1 Figure 1 Z08617 Functional Block Diagram ...

Page 3: ... P10 Port 1 Pins 0 1 2 3 4 5 6 7 In Output 29 P34 Port 3 Pin 4 Output 30 P33 Port 3 Pin 3 Input 31 38 P27 P20 Port 2 Pins 0 1 2 3 4 5 6 7 In Output 34 38 P24 P20 Port 2 Pins 0 1 2 3 4 In Output 39 P31 Port 3 Pin 1 Input 40 P36 Port 3 Pin 6 Output Table 1 40 Pin DIP Pin Identification 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VCC CLK Out RC In P37 P30 RESET GND N C WDTOUT P35 GND P32 P00 P...

Page 4: ...ondition above those indicated in the operational sections of these specifications is not implied Exposure to absolute maximum rating condi tions for extended periods may affect device reliabil ity STANDARD TEST CONDITIONS The characteristics listed here apply for standard test conditions as noted All voltages are referenced to GND Positive current flows into the referenced pin Figure 17 From Outp...

Page 5: ...eakage 10 10 µA VIN 0V 5 25V See note 3 below IOL Output Leakage 10 10 µA VIN 0V 5 25V See note 2 below IIR Reset Input Current 335 775 477 µA VIN 0V 5 25V IR1 Input Current 335 775 µA Pull up resistor 10 4 Kohms VIN 0 0V IR2 Input Current 1 6 2 9 mA Pull up resistor 2 4 Kohms VIN 0 0V ICC VCC Supply Current 160 mA WDT Watch Dog Timer 2 0 mA VOL 0 4 Volt Notes Typical 25 C 1 Ports P37 P34 may be u...

Page 6: ...r frequency Port 0 P07 P00 Port 0 is an 8 bit nibble program mable bi directional NMOS compatible I O port These eight I O lines can be configured under software control as a nibble input port or as a nibble open drain output port When used as an I O port inputs are standard NMOS Figure 5 Port P03 P00 has 10 4 Kohms 35 pull up resistors when configured as inputs Figure 5 Port 0 Configuration Port ...

Page 7: ...rammable bidirectional NMOS compatible I O port These eight I O lines are configured under software control program as a byte input port or as an open drain output port When used as an I O port inputs are standard NMOS Figure 6 Port 1 I O Open Drain Output Z8615 8 Input Output Pad OEN Figure 6 Port 1 Configuration ...

Page 8: ...y bit indepen dently as input or output or configured to provide open drain outputs Figure 7 P26 and P27 have 2 4 Kohms 25 pull up resistors and are capable of sourcing 2 4 mA P24 and P25 have 10 4 Kohms 35 pull up when configured as inputs Open Drain OUT OEN IN Pad Input a Ports P20 P23 Port 2 I O Z8615 Open Drain OUT OEN IN Pad 10 4 Kohms Input b Ports P24 P25 Open Drain OUT OEN IN Pad 2 4 Kohms...

Page 9: ...under software control to provide the following control functions four external interrupt request signals IRQ3 IRQ0 timer input and output signals TIN and TOUT Figure 8 RESET input active Low When activated RESET initializes the Z08617 When RESET is deactivated program execution begins from the internal program location at 000CH Reset pin has a 10 4 Kohms pull up resistor Once this pin is pulled L...

Page 10: ... Figure 9 The first 12 bytes of program memory are reserved for the interrupt vectors These locations have six 16 bit vectors that correspond to the six available interrupts Byte 12 to byte 4095 consists of on chip mask programmed ROM Addresses 4096 and greater are reserved 12 11 10 9 8 7 6 5 4 3 2 1 0 On Chip ROM Location of First Byte of Instruction Executed After RESET Interrupt Vector Lower By...

Page 11: ...General Purpose Register Bits 7 0 Register Pointer Program Control Flags Interrupt Mask Register Interrupt Request Register Interrupt Priority Register Ports 1 0 Mode Port 3 Mode Port 2 Mode T0 Prescaler Timer Counter0 T1 Prescaler Timer Counter1 Timer Mode Reserved Not Implemented General Purpose Registers Port 3 Port 2 Port 1 Port 0 R254 R253 R252 R251 R250 R249 R248 R247 R246 R245 R244 R243 R24...

Page 12: ... or to automatically reload the initial value and continue counting modulo n continuous mode The counters but not the prescalers are read at any time without disturbing their value or count mode The clock source for T1 is user definable and are either the internal microprocessor clock divided by four or an external signal input through Port 3 The Timer Mode register configures the external timer i...

Page 13: ...rrupt Priority register All inter rupts are vectored through locations in the program memory When an interrupt machine cycle is activated an interrupt request is granted This disables all of the subse quent interrupts saves the Program Counter and status flags and then branches to the program memory vector location reserved for that interrupt This memory location andthenextbytecontainthe16 bitaddr...

Page 14: ...onfiguration A 1 precision resistor is necessary to achieve 10 accurate frequency oscillation Figure 14 Oscillator Configuration EMI The Z08617 offers low EMI emission due to circuit modifications to improve EMI performance The inter naldivide by twocircuithasbeenremovedtoimproveEMI performance RC Oscillator XTAL1 NC 1 Precision XTAL2 5V ...

Page 15: ...t Dur ing WDT time out the WDTOUT pin goes Low for approximately 8 15 µs WDT Hot Bit Bit 7 of the Interrupt Request Register IRR register FAH determines whether a hot start or cold start occurred A cold start is defined as a rest occurring from the power up of the Z08617 bit 7 is set to zero upon power up A hot start occurs when a WDT time out has occurred bit 7 is set to 1 Bit 7 of the IRQ regist...

Page 16: ...ode 0 T1 Single Pass 1 T1 Modulo N Clock Source 1 T0 Internal 0 T0 External Timing Input TIN Mode Prescaler Modulo Range 1 64 Decimal 01 00 HEX R243 PRE1 Figure 20 Prescaler 1 Register F3H Write Only D7 D6 D5 D4 D3 D2 D1 D0 T0 Initial Value When WRITE Range 1 256 Decimal 01 00 HEX T0 Current Value When READ R244 T0 Figure 21 Counter Timer 0 Register F4H Read Write D7 D6 D5 D4 D3 D2 D1 D0 Count Mod...

Page 17: ...roup A 0 IRQ5 IRQ3 1 IRQ3 IRQ5 IRQ0 IRQ2 Priority Group B 0 IRQ2 IRQ0 1 IRQ0 IRQ2 IRQ1 IRQ4 Priority Group C 0 IRQ1 IRQ4 1 IRQ4 IRQ1 Reserved Must be 0 R249 IPR Figure 26 Interrupt Priority Register F9H Write Only D7 D6 D5 D4 D3 D2 D1 D0 Reserved Must be 0 1 Enables IRQ0 IRQ5 D0 IRQ0 1 Enables Interrupts R251 IMR Figure 28 Interrupt Mask Register FBH Read Write Figure 27 Interrupt Request Register...

Page 18: ...rry Flag R252 Flags Figure 29 Flag Register FCH Read Write D7 D6 D5 D4 D3 D2 D1 D0 Reserved Must be 0 r4 R253 RP r5 r6 r7 Register Pointer Figure 30 Register Pointer FDH Read Write D7 D6 D5 D4 D3 D2 D1 D0 GPR R254 GPR Figure 31 General Purpose Register FEH Read Write D7 D6 D5 D4 D3 D2 D1 D0 Stack Pointer Lower Byte SP0 SP7 R255 SPL Figure 32 Stack Pointer FFH Read Write ...

Page 19: ...ister address Ir Indirect working register address only RR Register pair or working register pair address Symbols The following symbols are used in describing the instruction set Symbol Meaning dst Destination location or contents src Source location or contents cc Condition code Indirect address prefix SP Stack Pointer PC Program Counter FLAGS Flag register Control Register 252 RP Register Pointe...

Page 20: ...00 OV Overflow V 1 1100 NOV No Overflow V 0 0110 EQ Equal Z 1 1110 NE Not Equal Z 0 1001 GE Greater Than or Equal S XOR V 0 0001 LT Less than S XOR V 1 1010 GT Greater Than Z OR S XOR V 0 0010 LE Less Than or Equal Z OR S XOR V 1 1111 UGE Unsigned Greater Than or Equal C 0 0111 ULT Unsigned Less Than C 1 1011 UGT Unsigned Greater Than C 0 AND Z 0 1 0011 ULE Unsigned Less Than or Equal C OR Z 1 000...

Page 21: ... dst dst src OPC VALUE dst OPC RA dst CC 7FH FFH 6FH OPC dst dst src 1 1 1 0 dst 1 1 1 0 src 1 1 1 0 MODE src OPC dst MODE dst OPC VALUE OPC src MODE dst OPC MODE ADDRESS x dst src OPC DAU cc DAL DAU DAL OPC src 1 1 1 0 dst 1 1 1 0 dst 1 1 1 0 src 1 1 1 0 dst 1 1 1 0 CLR CPL DA DEC DECW INC INCW POP PUSH RL RLC RR RRC SRA SWAP JP CALL Indirect OR OR OR OR OR OR OR SRP ADC ADD AND CP OR SBC SUB TCM...

Page 22: ... dst dst 1 IR 0 1 DECW dst RR 8 0 dst dst 1 IR 8 1 DI 8F IMR 7 0 DJNZr dst RA rA r r 1 r 0 F if r 0 PC PC dst Range 127 128 EI 9F IMR 7 1 Address Flags Instruction Mode Opcode Affected and Operation dst src Byte Hex C Z S V D H INC dst r rE dst dst 1 r 0 F R 2 0 IR 2 1 INCW dst RR A 0 dst dst 1 IR A 1 IRET BF FLAGS SP SP SP 1 PC SP SP SP 2 IMR 7 1 JP cc dst DA CD if cc is true C 0 F PC dst IRR 3 0...

Page 23: ... C 0 RET AF PC SP SP SP 2 RL dst R 9 0 IR 9 1 RLC dst R 1 0 IR 1 1 RR dst R E0 IR E1 RRC dst R C0 IR C1 SBC dst src 3 1 dst dst src C SCF DF 1 C 1 SRA dst R D0 0 IR D1 SRP src Im 3 1 RP src C 7 0 C 7 0 C 7 0 C 7 0 C 7 0 These instructions have an identical set of addressing modes which are encoded for brevity The first opcode nibble is found in the instruction set table above The second nibble is ...

Page 24: ...10 5 LD IR2 R1 10 5 LD R1 IM 10 5 LD IR1 IM 8 5 SWAP R1 8 5 SWAP IR1 6 5 LD Ir1 r2 10 5 LD R2 IR1 6 5 LD r1 R2 6 5 LD r2 R1 12 10 5 DJNZ r1 RA 12 10 0 JR cc RA 6 5 LD r1 IM 12 10 0 JP cc DA 6 5 INC r1 6 1 DI 6 1 EI 14 0 RET 16 0 IRET 6 5 RCF 6 5 SCF 6 5 CCF 6 0 NOP 10 5 CP R R 1 2 4 A Lower Opcode Nibble Pipeline Cycles Mnemonic Second Operand Execution Cycles Upper Opcode Nibble First Operand Leg...

Page 25: ...25 Z08617 NMOS Z8 8 BIT MCU KEYBOARD CONTROLLER PACKAGE INFORMATION 40 Pin DIP Package Diagram ...

Page 26: ... part desired Package P Plastic DIP V Plastic Leaded Chip Carrier Speed 05 5 MHz Environmental C Plastic Standard Temperature S 0 C to 70 C standard temp for the Z8615 is 0 to 55 C Example Z 8615 05 P S C Environmental Flow T emperature standard temp for the Z8615 is 0 to 55 C Package Speed Product Number Zilog Prefix is a Z8615 5 MHz DIP 0 C to 55 C Plastic Standard Flow ...

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